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Intel BX80539T2500 User Manual - Page 40

Intel BX80539T2500 - Core Duo 2 GHz Processor Manual

UPC - 735858180054

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4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with IntelD®eEv7e5lo2p0mCehnipt sKeitt S3 State TDctP4shoeoh5Reqnwi0AsutSeMiWsenrLtn,uPamSceb_teeS.uuSItsAt3isotpl1#lbco2ecaeswnlVolitlgesecerwnpkdraosiisStSlwcsutushetoshsoerppupddseetounefnworpxddofpncfmttelstyootporttdRRehnoAtAaeohemMMnens-oi(cRncsrSiroTrmiTacttCRisuac.d)ilafitS.or1rle3ylT.clc8ohiittrsweolcVyusesc:rsinyotaustsniep.tlterptrMemoolydelsmc1awtoa.oh8snnrtetydaVenbnxipsytdthobr1iewsey.t8eIma1/ri.VOan8p,ienlcbaVdtoena,nrceiaantarniseulo.dwdsllTeierithnerctefhhasrieeysnsssghet.eretmss 1. The OS and BIOS prepare for S3 sleep state. 2. The OS sets the appropriate sleep bits in the I/O controller. 3. The I/O controller drives STPCLK to the processor. 4. The processor respond with a Stop-Grant cycle, passed over hub interface by MCH. 5. ATh. e I/O controller indicates an S3 (STR) sleep mode to the MCH via Hub Interface 6. The MCH puts DDR memory into the self-refresh mode. 7. The MCH drives DDR CMDCLK differential pairs and all DDR outputs low. 8. The MCH drives a completion message via Hub Interface A to the I/O controller. 9. pTohwe eI/rOsucpopnltyroblylerastsuernrtsinogffthalel vSoLlPta_gSe3_raNilssig(enxacl.ept Standby 5 V) from the main Wbohaernd iunsethsethSi3s ssttaanted,boynslyouthrceesttoangdebnyer5atVe r1a.i8l iVs asvtaanildabbylerfariolmtotphoewpeorwtehresDuIpMpMly.s.The Tfrhoemamssaeirnte1d.8SLVPt_oSs3t_aNndsbigyn1a.l8alVs.o controls the logic to switch the DIMM power source S4 State This state is not supported. S5 State TASsuhl5lpispsptoslaywttaeiestreouinisnslpysthlhuwueghtgnioleoefdrfmt,ehtaxehclipesoopfifwstsefctoroarntsetsuhipwdepehllroyeegtdihisceaprrelmueqngeutgcierheredaedndinitctotaholrreotohsuffetgaoherrtlte.GhcTe3thr.piecoaswlyeostruetbmleuttr.teoImnf taohirnesspoiofntwtoehfrfe. Wake-Up Events TrwbtvchaaohuhierletlitdstcasothagytynovsepttaihewsetiesolmaaasokbelwyecflaesoacwutmyhteaposmkpPtstelChihuce-IeeupossppnsswlotyoyeeirststvxtthtaeeetesdmntmihstwesefsixernatPcololneCmaradpIepstdaswai.tpnnraheyRtkeiacecesiguPf-umiMulacpaerappErdct#oilshlaoerlaettnsseenesigndbipconycasfsiaellsttelsauo.hetfpeTapfephr,ssesliyilsatteiarusneeetagpnweltaaietsteobhetlxnlaledec.ateseotsWpo,patthtwnotiemhoyantenkhecaeiecaonlhcmol3taaonu.pnc3salaitilclaheVtainpeeolstopnpotwPaofsifCenntw.arIdetbery, Wake from S1 Sleep State DWuarkinegonS1PCthIePMsyEs#te.m is fully powered, permitting support for PCI Express* Wake and Wake from S3 State Keyboard press or mouse movement is used to wake from S3. Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit User's Manual January 2007 40 Order Number: 316068-001US

Section	Page
Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit	1
Contents	3
Figures	3
Tables	4
1.0 About This Manual	6
1.1 Content Overview	6
1.2 Text Conventions	6
1.3 Technical Support	7
1.3.1 Additional Technical Support	7
1.4 Product Literature	8
Table 1. Intel Literature Centers	8
1.5 Related Documents	8
Table 2. Related Documents	8
2.0 Getting Started	9
2.1 Overview	9
2.2 Evaluation Board Features	10
Table 3. Supported Processors	10
2.3 Included Hardware	11
2.4 Software Key Features	11
2.4.1 AMIBIOS* for the Development Kit	12
2.5 Before You Begin	12
Table 4. Additional Hardware	12
2.5.1 Setting up the Evaluation Board	12
Figure 1. Evaluation Board Before Installing Additional Hardware	13
2.5.2 Safety	13
2.5.3 Package Contents	14
2.5.4 Installed Hardware	14
2.5.5 Installing Standoffs	14
2.5.6 Installing the Heatsinks for Processor and MCH	14
Table 5. Heatsink Information	15
Figure 2. Location for the Processor, MCH, and PXH for Heatsink Installation	15
2.5.7 Processor Heatsink Installation	15
Figure 3. Processor Heatsink Top and Bottom View	16
Figure 4. Processor in Socket and Package Secured	16
Figure 5. Clean Top of Processor Die	17
Figure 6. Back Plate in Place	18
Figure 7. Heatsink Mounted on Processor	18
Figure 8. Screw Tightening Order	19
2.5.8 MCH Heatsink Installation	19
Figure 9. MCH Heatsink Top View	19
Figure 10. Clean Top of MCH Die	20
Figure 11. Hook Heatsink Clip to Anchor	20
Figure 12. Heatsink Fan Connector	21
2.5.9 Installing Memory	21
2.5.10 Installing Storage Devices	22
2.5.11 Connect the Monitor Cable	23
2.5.12 Connect the Keyboard and Mouse	23
2.5.13 Connect the Power Supply	23
2.5.14 Power the System	23
2.6 Configuring the BIOS	23
3.0 Theory of Operation	25
3.1 Block Diagram	25
Figure 13. Block Diagram of Layout	25
3.2 Thermal Management	25
3.3 System Features	26
3.3.1 Intel® Core™ 2 Duo Processor	27
3.3.2 Intel® Core™ Duo Processor	27
3.3.3 Intel® E7520 MCH	27
3.3.4 Intel® 6300ESB ICH	27
3.3.5 Intel® 6700PXH PCI Hub	28
3.3.6 Intel® 82571EB Gigabit Ethernet Controller	28
3.3.7 Memory Subsystem	28
3.3.8 Supported DIMM Module Types	29
Table 6. Supported DIMM Module Types	29
3.3.9 Memory Population Rules and Configurations	29
Figure 14. DDR2-400 Memory-DIMM Ordering	29
3.3.10 Firmware Hub (FWH)	30
3.3.11 Boot ROM	30
3.3.12 In-Target Probe (ITP)	30
Figure 15. ITP location	30
3.3.13 Power Diagram	31
Figure 16. Power Distribution Block Diagram	31
3.3.14 Clock Generation	32
Figure 17. Clock Block Diagram	32
3.3.15 Platform Resets	33
Figure 18. Platform Reset Diagram	33
3.3.16 SMBus	34
Figure 19. SMBus Block Diagram	34
3.3.17 Platform IRQ Routing	35
Figure 20. IRQ Routing Diagram	35
3.3.18 VRD VID Headers	36
Table 7. Processor VRD Settings	37
3.4 Battery Requirements	38
4.0 Platform Management	39
4.1 Power Button	39
4.2 Sleep States Supported	39
4.2.1 S0 State	39
4.2.2 S1 State	39
4.2.3 S2 State	39
4.2.4 S3 State	40
4.2.5 S4 State	40
4.2.6 S5 State	40
4.2.7 Wake-Up Events	40
4.2.8 Wake from S1 Sleep State	40
4.2.9 Wake from S3 State	40
4.2.10 Wake from S5 State	41
4.3 PCI PM Support	41
4.4 Platform Management	41
4.4.1 Processor Thermal Management	41
4.5 System Fan Operation	41
5.0 Driver and Operating System Support	42
5.1 Video Driver Issue	42
6.0 Hardware Reference	43
Figure 21. Evaluation Board	43
6.1 Chipset Components	44
Table 8. Chipset Components	44
6.2 Expansion Slots and Sockets	44
Table 9. Expansion Slots and Socket	44
6.2.1 PCI Express* Connector	44
Table 10. PCI Express* Port A (x8) Connector Pinout (Sheet 1 of 2)	44
Table 11. PCI Express* Port B (X4) Connector Pinout	46
6.2.2 32-Bit PCI Connector	47
Table 12. 32-Bit 5 V PCI Connector Pinout (Sheet 1 of 2)	47
6.2.3 PCI-X Connector	48
Table 13. PCI-X Connector Pinout (Sheet 1 of 4)	48
6.2.4 Processor Sockets	51
6.2.5 Firmware Hub (FWH) BIOS Socket	51
6.2.6 Battery	51
6.3 On-Board Connectors	51
Table 14. On-Board Connector	51
6.3.1 SATA Connector	52
Table 15. SATA Connector Pinout	52
6.3.2 IDE Connector	52
Table 16. IDE Connector Pinout	52
6.3.3 Floppy Drive Connector	53
Table 17. Floppy Drive Connector Pinout	53
6.3.4 Front Panel Connector	53
Table 18. Front Panel Connector Pinout	53
6.4 Jumpers	54
Table 19. Jumpers and Descriptions	54
Figure 22. Key Jumper Locations	56
6.5 SMBUS Headers	57
Table 20. SMBUS 3.3 V STBY Pinout	57
6.6 Back Panel Connectors	57
Figure 23. Back Panel Connectors	57
6.6.1 PS/2* Mouse and Keyboard Connectors	57
Table 21. PS/2* Mouse and Keyboard Pinout	57
6.6.2 Parallel Port	58
Table 22. Parallel Port Connector Pinout	58
6.6.3 Serial Ports	58
Table 23. Serial Port Connector Pinout	58
6.6.4 Dual Stacked USB Connectors	59
Table 24. USB Connector Pinout	59
6.6.5 Video Port	59
Table 25. Video Port Connector Pinout	59
6.6.6 Dual Gigabit Ethernet Ports	59
Table 26. Dual Gigabit Ethernet Port Connector Pinout (Sheet 1 of 2)	59
7.0 Board Setup Checklist	61
8.0 Debug Procedure	62
8.1 Level 1 Debug (Port80/BIOS)	62
Table 27. Level 1 Debug (Port80/BIOS)	62
8.2 Level 2 Debug (Power Sequence)	62
Table 28. Level 2 Debug (Power Sequence)	62
8.3 Level 3 Debug (Voltage References)	63

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