Intel BX80539T2500 User Manual - Page 56
J9G3/J9G4, J5E3/J5F6, J4H2/J4J2
UPC - 735858180054
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Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with IntelD®eEv7e5lo2p0mCehnipt sKeitt Table 19. Jumpers and Descriptions Jumper Description / Settings Default Position J(L5AAN1_(A3U.3XVPWSuRp_pSlyT)R,AJP5)A,2 J6B1 (ICH_Wake) J8H2 J7J2 LAN Wake On Control (J5A1/J5A2/J6B1/Lan Wake On Status) 1-2/1-2/1-2/Wake On 2-3/2-3/1-2/No Wake On DDR S3 Enable BCKFD_CT_LTCH Short: Enable DIMM S3 Open: Disable DIMM S3 Processor ThermDA and ThermDC External connection 2: Thermal DA connection 3: Ground J5A1: 2-3 J5A2: 2-3 J6B1: 1-2 1-2 Open Figure 22. Key Jumper Locations J1A1 J3A1 J4A1 J2G3 J4H2/J4J2 J2J1 J5E3/J5F6 J5H2 J9G3/J9G4 J8H2 J8H3 Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit User's Manual January 2007 56 Order Number: 316068-001US