Intel DX79SI Intel Desktop Board DX79SI Technical Product Specification - Page 80
Table 41., Port 80h POST Codes
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Intel Desktop Board DX79SI Technical Product Specification Table 41. Port 80h POST Codes Port 80 Code Progress Code Enumeration 0x00,0x01,0x02,0x03,0x04,0x05 0x10,0x20,0x30,0x40,0x50 0x08 0x09 ACPI S States Entering S0, S2, S3, S4, or S5 state Resuming from S2, S3, S4, S5 Security Phase (SEC) Starting BIOS execution after CPU BIST SPI prefetching and caching 0x0A Load BSP microcode 0x0B Load APs microcodes 0x0C Platform program baseaddresses 0x0D Wake Up All APs 0x0E Initialize NEM 0x0F Pass entry point of the PEI core PEI before MRC 0x11 0x12 PEI Platform driver Set bootmode, GPIO init Early chipset register programming including graphics init 0x13 0x14 0x15 Basic PCH init, discrete device init (1394, SATA) LAN init Exit early platform init driver PEI SMBUS 0x16 SMBUSriver init 0x17 Entry to SMBUS execute read/write 0x18 Exit SMBUS execute read/write PEI CK505 Clock Programming 0x19 Entry to CK505 programming 0x1A Exit CK505 programming PEI Over-Clock Programming 0x1B Entry to entry to PEI over-clock programming 0x1C Exit PEI over-clock programming 0x21 0x23 Memory MRC entry point Reading SPD from memory DIMMs 0x24 0x27 0x28 Detecting presence of memory DIMMs Configuring memory Testing memory 0x29 Exit MRC driver PEI after MRC 0x2A Start to Program MTRR Settings 0x2B Done Programming MTRR Settings continued 80