Intel E5345 Specification Update - Page 14

Errata (Sheet 5 of 6) Number Steppings B-3 G-0 AJ97 X AJ98 X X AJ99 X X AJ100 X X AJ101 X AJ102 X X AJ103 X X AJ104 X AJ105 X X AJ106 X X AJ107 X AJ108 X X AJ109 X X AJ110 X AJ111 X X AJ112 X X AJ113 X X AJ114 X X Status Plan Fix No Fix No Fix No Fix Plan Fix No Fix No Fix Plan Fix No Fix No Fix Plan Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix AJ115 X X No Fix AJ116 X X No Fix AJ117 X X No Fix AJ118 X X No Fix AJ119 X Fixed AJ120 X X No Fix AJ121 X X No Fix AJ122 X X No Fix ERRATA Processor On Die Termination of BR1# and LOCK# Signals are Incorrect Store Ordering May be Incorrect between WC and WP Memory Types Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code #PF Performance Monitoring Event CPU_CLK_UNHALTED.REF May Not Count Clock Cycles According to the Processors Operating Frequency Performance Monitoring Event BR_INST_RETIRED May Count CPUID Instructions as Branches Performance Monitoring Event MISALIGN_MEM_REF May Over Count A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR Information Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior Dual-Processor Incompatibility Between B-step and G-step VTPR Write Access During Event Delivery May Cause an APIC-Access VM Exit BIST Failure After Reset Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-Ordering Violations VM Exit with Exit Reason "TPR Below Threshold" Can Cause the Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility-State Field Using Memory Type Aliasing with cacheable and WC Memory Types May Lead to Memory Ordering Violations VM Exit due to Virtual APIC-Access May Clear RF RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results NMIs May Not Be Blocked by a VM-Entry Failure Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010