Intel E5345 Specification Update - Page 25

AJ26. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the below circumstances occur, it is possible that the load portion of the instruction will have executed before the exception handler is entered. • If an instruction that performs a memory load causes a code segment limit viola- tion. • If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX) instruc- tion that performs a memory load has a floating-point exception pending. • If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point Topof-Stack (FP TOS) not equal to 0, or a DNA exception pending. Implication: In normal code execution where the target of the load operation is to write back memory there is no impact from the load being prematurely executed, or from the restart and subsequent re-execution of that instruction by the exception handler. If the target of the load is to uncached memory that has a system side-effect, restarting the instruction may cause unexpected system behavior due to the repetition of the sideeffect. Particularly, while CR0.TS [bit 3] is set, a MOVD/MOVQ with MMX/XMM register operands may issue a memory load before getting the DNA exception. Workaround: Code which performs loads from memory that has side-effects can effectively workaround this behavior by using simple integer-based load instructions when accessing side-effect memory and by ensuring that all code is written such that a code segment limit violation cannot occur as a part of reading from side-effect memory. Status: For the steppings affected, see the Summary Tables of Changes. AJ27. General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit Problem: In 32-bit mode, memory accesses to flat data segments (base = 00000000h) that occur above the 4G limit (0ffffffffh) may not signal a #GP fault. Implication: When such memory accesses occur in 32-bit mode, the system may not issue a #GP fault. Workaround: Software should ensure that memory accesses in 32-bit mode do not occur above the 4G limit (0ffffffffh). Status: For the steppings affected, see the Summary Tables of Changes. AJ28. EIP May be Incorrect after Shutdown in IA-32e Mode Problem: When the processor is going into shutdown state the upper 32 bits of the instruction pointer may be incorrect. This may be observed if the processor is taken out of shutdown state by NMI#. Implication: A processor that has been taken out of the shutdown state may have an incorrect EIP. The only software which would be affected is diagnostic software that relies on a valid EIP. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ29. #GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34] When Execute Disable Bit is Not Supported Problem: A #GP fault is not generated on writing to IA32_MISC_ENABLE [34] bit in a processor which does not support Execute Disable Bit functionality. Implication: Writing to IA32_MISC_ENABLE [34] bit is silently ignored without generating a fault. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5300 Series 25 Specification Update, December 2010