Intel E5345 Specification Update - Page 44

AJ103. A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware Problem: The MONITOR instruction is used to arm the address monitoring hardware for the subsequent MWAIT instruction. The hardware is triggered on subsequent memory store operations to the monitored address range. Due to this erratum, REP STOS/MOVS fast string operations to the monitored address range may prevent the actual triggering store to be propagated to the monitoring hardware. Implication: A logical processor executing an MWAIT instruction may not immediately continue program execution if a REP STOS/MOVS targets the monitored address range. Workaround: Software can avoid this erratum by not using REP STOS/MOVS store operations within the monitored address range Status: For the steppings affected, see the Summary Tables of Changes. AJ104. False Level One Data Cache Parity Machine-Check Exceptions May be Signaled Problem: Executing an instruction stream containing invalid instructions/data may generate a false Level One Data Cache parity machine-check exception. Implication: The false Level One Data Cache parity machine-check exception is reported as an uncorrected machine-check error. An uncorrected machine-check error is treated as a fatal exception by the operating system and may cause a shutdown and/or reboot. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AJ105. A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask Problem: The TLB (Translation Lookaside Buffer) may indicate a wrong memory type on a memory access to a large page (2M/4M Byte) following the recovery from a #GP (General Protection Fault) due to a WRMSR to one of the IA32_MTRR_PHYSMASKn MSRs with reserved bits set. Implication: When this erratum occurs, a memory access may get an incorrect memory type leading to unexpected system operation. As an example, an access to a memory mapped I/O device may be incorrectly marked as cacheable, become cached, and never make it to the I/O device. Intel has not observed this erratum with any commercially available software. Workaround: Software should not attempt to set reserved bits of IA32_MTRR_PHYSMASKn MSRs. Status: For the steppings affected, see the Summary Tables of Changes. AJ106. PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR Information Problem: When Precise Event-Based Sampling (PEBS) is configured with Performance Monitoring Interrupt (PMI) on PEBS buffer overflow enabled and Last Branch Record (LBR) Freeze on PMI enabled by setting FREEZE_LBRS_ON_PMI flag (bit 11) to 1 in IA32_DEBUGCTL (MSR 1D9H), the LBR stack is frozen upon the occurrence of a hardware PMI request. Due to this erratum, the LBR freeze may occur too soon (i.e. before the hardware PMI request). Implication: Following a PMI occurrence, the PMI handler may observe old/out-of-date LBR information that does not describe the last few branches before the PEBS sample that triggered the PMI. Workaround: None Identified. Status: For the steppings affected, see the Summary Tables of Changes. 44 Intel® Xeon® Processor 5300 Series Specification Update, December 2010