Intel E5345 Specification Update - Page 42

buffer. The information in the PEBS record represents the state of the next instruction to be executed following the counter overflow. Due to this erratum, if the counter overflow occurs after execution of either MOV SS or STI, storage of the PEBS record is delayed by one instruction. Implication: When this erratum occurs, software may observe storage of the PEBS record being delayed by one instruction following execution of MOV SS or STI. The state information in the PEBS record will also reflect the one instruction delay. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ97. Processor On Die Termination of BR1# and LOCK# Signals are Incorrect Problem: On Die Termination control of BR1# and LOCK# signals are incorrect. BR#1 has its On Die Termination continuously enabled and LOCK# has its On Die Termination continuously disabled. Implication: BR1# has its On Die Termination continuously enabled meaning the VOL (Output Low Voltage) of this signal is expected to be higher than normal losing potential margin for nominal VCCP. LOCK# has its On Die Termination always disabled meaning the VOL of this signal is expected to be lower than normal and could lead to signal degradation. Even if the BR1# and Lock# terminations are always on or always off, VOL electrical specifications are not violated. Intel has not observed any functional failure due to this erratum. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ98. Ordering May be Incorrect between WC and WP Memory Types Problem: According to Intel® 64 and IA-32 Intel Architecture Software Developer's Manual, Volume 3A "Methods of Caching Available", WP (Write Protected) stores should drain the WC (Write Combining) buffers in the same way as UC (Uncacheable) memory type stores do. Due to this erratum, WP stores may not drain the WC buffers. Implication: Memory ordering may be violated between WC and WP stores. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AJ99. Problem: Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code #PF Code #PF (Page Fault exception) is normally handled in lower priority order relative to both code #DB (Debug Exception) and code Segment Limit Violation #GP (General Protection Fault). Due to this erratum, code #PF may be handled incorrectly, if all of the following conditions are met: • A PDE (Page Directory Entry) is modified without invalidating the corresponding TLB (Translation Look-aside Buffer) entry • Code execution transitions to a different code page such that both - The target linear address corresponds to the modified PDE - The PTE (Page Table Entry) for the target linear address has an A (Accessed) bit that is clear • One of the following simultaneous exception conditions is present following the code transition - Code #DB and code #PF - Code Segment Limit Violation #GP and code #PF 42 Intel® Xeon® Processor 5300 Series Specification Update, December 2010