MSI 845GEM-L User Guide - Page 53

Advanced Chipset Features, Con DRAM Timing, CAS# Latency, Precharge Delay

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845 GM/GLM/GEM/PEM/GVM series M-ATX Mainboard Advanced Chipset Features MSI Reminds You... Change these settings only if you are familiar with the chipset. Configure DRAM Timing Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect) EEPROM on the DRAM module. Setting to By SPD enables DRAM timings to be determined by BIOS based on the configurations on the SPD. Selecting Manual allows users to configure the DRAM timings manually. CAS# Latency This controls the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. Settings: 1.5, 2, 2.5, 3 (clocks). 1.5 (clocks) increases the system performance the most while 3 (clocks) provides the most stable performance. Precharge Delay The field specifies the idle cycles before precharging an idle bank. Settings: 7, 6, 5 (clocks). RAS# to CAS# Delay This field allows you to set the number of cycles for a timing delay 3-12

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3-12
845 GM/GLM/GEM/PEM/GVM series M-ATX Mainboard
Advanced Chipset Features
MSI Reminds You...
Change these settings only if you are familiar with the chipset.
Configure DRAM Timing
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module.
Setting to
By SPD
enables DRAM
timings to be determined by BIOS based on the configurations on the SPD.
Selecting
Manual
allows users to configure the DRAM timings manually.
CAS# Latency
This controls the timing delay (in clock cycles) before SDRAM starts a
read command after receiving it.
Settings:
1.5
,
2
,
2.5, 3
(clocks).
1.5
(clocks) increases the system performance the most while
3
(clocks)
provides the most stable performance.
Precharge Delay
The field specifies the idle cycles before precharging an idle bank.
Settings:
7
,
6
,
5
(clocks).
RAS# to CAS# Delay
This field allows you to set the number of cycles for a timing delay