MSI 845GEM-L User Guide - Page 65

IRQ Resources, PCI/VGA Palette Snoop, VGA Palette, Snoop Bit Setting, Action, Resources Controlled

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845 GM/GLM/GEM/PEM/GVM series M-ATX Mainboard IRQ Resources The items are adjustable only when Resources Controlled By is set to Manual. Press and you will enter the sub-menu of the items. IRQ Resources list IRQ 3/4/5/7/9/10/11/12/14/15 for users to set each IRQ a type depending on the type of device using the IRQ. Settings are: PCI Device Reserved For Plug & Play compatible devices designed for PCI bus architecture. The IRQ will be reserved for further request. PCI/VGA Palette Snoop When set to Enabled, multiple VGA devices operating on different buses can handle data from the CPU on each set of palette registers on every video device. Bit 5 of the command register in the PCI device configuration space is the VGA Palette Snoop bit (0 is disabled). For example, if there are two VGA devices in the computer (one PCI and one ISA) and the: VGA Palette Snoop Bit Setting Action Disabled Data read or written by the CPU is only directed to the PCI VGA device's palette registers. Enabled Data read or written by the CPU is directed to both the PCI VGA device's palette registers and the ISA VGA device's palette registers, permitting the palette registers of both VGA devices to be identical. The setting must be set to Enabled if any ISA bus adapter in the system requires VGA palette snooping. 3-24

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3-24
845 GM/GLM/GEM/PEM/GVM series M-ATX Mainboard
IRQ Resources
The items are adjustable only when
Resources Controlled By
is set to
Manual
.
Press <Enter> and you will enter the sub-menu of the items.
IRQ Resources list IRQ 3/4/5/7/9/10/11/12/14/15 for users to set each IRQ a
type depending on the type of device using the IRQ. Settings are:
PCI Device
For Plug & Play compatible devices designed for PCI
bus architecture.
Reserved
The IRQ will be reserved for further request.
PCI/VGA Palette Snoop
When set to
Enabled
, multiple VGA devices operating on different buses can
handle data from the CPU on each set of palette registers on every video
device. Bit 5 of the command register in the PCI device configuration space is
the VGA Palette Snoop bit (0 is disabled).
For example, if there are two VGA
devices in the computer (one PCI and one ISA) and the:
The setting must be set to
Enabled
if any ISA bus adapter in the system requires
VGA palette snooping.
VGA Palette
Snoop Bit Setting
Action
Disabled
Data read or written by the CPU is only directed to the
PCI VGA device’s palette registers.
Enabled
Data read or written by the CPU is directed to both the
PCI VGA device’s palette registers and the ISA VGA
device’s palette registers, permitting the palette registers
of both VGA devices to be identical.