Pioneer 434CMX Service Manual - Page 145

Output Pins, Differential Signal Data Pins, Pin Name, Function

Get Pioneer 434CMX - PDP - 43inch Plasma Panel PDF manuals and user guides
UPC - 012562691107
View all Pioneer 434CMX manuals
Add to My Manuals
Save this manual to your list of manuals

Page 145 highlights

5 6 7 8 Pin Function Output Pins Pin Name No. QE23 - QE0 37-30, 27-20, 17-10 QO23 - QO0 ODCK DE HSYNC VSYNC CTL1 CTL2 CTL3 77, 75-69, 66-59, 56-49 44 46 48 47 40 41 42 Type Function A Output Even Data[23:0] corresponds to 24-bit pixel data for one pixel per clock input mode and to the first 24-bit pixel data for two pixels per clock mode. Output data is synchronized with output data clock (ODCK). Out Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the input data to the transmitter and output data from the receiver. A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. Output Odd Data[23:0] corresponds to the second 24-bit pixel data for two pixels per clock mode. During one pixel per clock mode, these outputs are driven low. Output data is synchronized with output data clock (ODCK). Out Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the input data to the transmitter and output data from the receiver. A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode. B A weak internal pull-down device brings each output to ground. Output Data Clock. This output can be inverted using the OCK_INV pin. A low level on PD# or Out PDO# will put the output driver into a high impedance (tri-state) mode. A weak internal pulldown device brings the output to ground. Output Data Enable. This signal qualifies the active data area. A HIGH level signifies active Out display time and a LOW level signifies blanking time. This output signal is synchronized with the output data. A low level on PD# or PDO# will put the output driver into a high impedance (tri-state) mode. A weak internal pull-down device brings the output to ground. Horizontal Sync output control signal. Vertical Sync output control signal. General output control signal 1. This output is not powered down by PDO#. Out General output control signal 2. C General output control signal 3. A low level on PD# or PDO# will put the output drivers (except CTL1 by PDO#) into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. Differential Signal Data Pins Pin Name No. Type Function RX0+ RX0RX1+ RX1RX2+ RX2- 90 91 85 86 Analog Receiver Differential Data Pins. TMDS Low Voltage Differential Signal input data pairs. 80 D 81 RXC+ RXC- 93 94 Analog Receiver Differential Clock Pins. TMDS Low Voltage Differential Signal input clock pair. EXT_RES 96 Analog Impedance Matching Control. An external 390Ω resistor must be connected between AVCC and this pin. E F PDP-434CMX 145 5 6 7 8

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
PDP-434CMX
145
5
6
7
8
5
6
7
8
C
D
F
A
B
E
Output Pins
Differential Signal Data Pins
Pin Name
No.
Type
Function
QE23 - QE0
37-30,
27-20,
17-10
Out
Output Even Data[23:0] corresponds to 24-bit pixel data for one pixel per clock input mode and to
the first 24-bit pixel data for two pixels per clock mode.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the input
data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
QO23 - QO0
77,
75-69,
66-59,
56-49
Out
Output Odd Data[23:0] corresponds to the second 24-bit pixel data for two pixels per clock mode.
During one pixel per clock mode, these outputs are driven low.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the
input data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
ODCK
44
Out
Output Data Clock. This output can be inverted using the OCK_INV pin. A low level on PD# or
PDO# will put the output driver into a high impedance (tri-state) mode. A weak internal pulldown
device brings the output to ground.
DE
46
Out
Output Data Enable. This signal qualifies the active data area. A HIGH level signifies active
display time and a LOW level signifies blanking time. This output signal is synchronized with
the output data. A low level on PD# or PDO# will put the output driver into a high impedance
(tri-state) mode. A weak internal pull-down device brings the output to ground.
HSYNC
VSYNC
CTL1
CTL2
CTL3
48
47
40
41
42
Out
Horizontal Sync output control signal.
Vertical Sync output control signal.
General output control signal 1. This output is not powered down by PDO#.
General output control signal 2.
General output control signal 3.
A low level on PD# or PDO# will put the output drivers (except CTL1 by PDO#) into a high
impedance (tri-state) mode. A weak internal pull-down device brings each output to ground.
Pin Name
No.
Type
Function
RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
90
91
85
86
80
81
Analog
Receiver Differential Data Pins. TMDS Low Voltage Differential Signal input data pairs.
RXC+
RXC-
93
94
Analog
Receiver Differential Clock Pins. TMDS Low Voltage Differential Signal input clock pair.
EXT_RES
96
Analog
Impedance Matching Control. An external 390
Ω
resistor must be connected between AVCC
and this pin.
Pin Function