Pioneer DVL-909 Service Guide - Page 41

Pioneer DVL-909 Manual

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DV-505, DVL-909, DV-S9 No. Pin Name 53 DAIIN 54 CDDATA 55 CDLR 56 CDBCK 57 AODATA3 58 AODATA2 59 AODATA1 60 VSS 61 VDD 62 AODATA0 63 AOPCM 64 AODAI 65 LRCK 66 AOMCK 67 BCK 68 ICED1 69 ICED0 70 ICEBRK 71 XDSPRST 72 VSS 73 N.C. 74 TEST2 75 TEST3 76 TEST4 77 TEST5 78 SD7 79 VDD 80 SD6 81 SD5 82 SD4 83 SD3 I/O Function I Digital data input of external input (SPDIF) I Audio data input of external input (correspond to CD) I Data channel clock input of external input (correspond to CD) I Data clock input of external input (correspond to CD) O Audio decode data − GND − 3.3V power supply O Audio decode data O Digital audio interface output (compression data) O Digital audio interface output (decode data) O Data channel clock for D/A and digital filter O Master clock for D/A and digital filter O Bit clock for D/A and digital filter − Pin for emulator Normally, set to "open". − GND − Non connection − Normally, set to "open". I Parallel data input − 3.3V power supply I Parallel data input 84 SD2 85 VSS 86 SD1 87 SD0 88 XERR 89 XSACK 90 XTEST 91 SREQ − GND I Parallel data input I Error input signal I Acknowledge signal I Set to "H" at normal use O Data request signal No. Pin Name I/O Function 92 HADRS10 I CPU address bus signal (MSB) 93 HADRS9 94 HADRS8 I CPU address bus signal 95 HADRS7 96 VSS 97 VDD 98 HADRS6 99 HADRS5 100 HADRS4 101 HADRS3 − GND − 3.3V power supply CPU address bus signal I 102 HADRS2 CPU address bus signal (LSB) 103 HDATA15 104 HDATA14 105 HDATA13 106 HDATA12 107 VSS 108 HDATA11 109 HDATA10 110 HDATA9 111 HDATA8 112 HDATA7 113 HDATA6 114 VDD 115 HDATA5 116 HDATA4 117 HDATA3 118 HDATA2 119 VSS 120 HDATA1 121 HDATA0 122 BUSSEL 123 XOSDACK 124 XOSDREQ 125 HCPUSEL1 126 HCPUSEL0 127 XINT3 128 XINT2 129 XINT1 130 VSS CPU data bus signal (MSB) I/O CPU data bus signal − GND I/O CPU data bus signal − 3.3V power supply I/O CPU data bus signal − GND CPU data bus signal I/O CPU data bus signal (LSB) I Bus width selection signal (0 : 8-bit bus, 1 : 16-bit bus) I OSD data acknowledge signal O OSD data request signal I CPU selection signal (00 :SPARC, 01 :86 system, 10 :68 system, 11 :Reserve) O Interrupt request signal to the CPU − GND 41

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