ASRock Fatal1ty X399 Professional Gaming User Manual - Page 89

Platform first Error Handling, Global C-state Control

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Fatal1ty X399 Professional Gaming Series Custom Pstates5 Custom P-State5 or leave this item to [Auto]. Custom Pstates6 Custom P-State6 or leave this item to [Auto]. Custom Pstates7 Custom P-State7 or leave this item to [Auto]. Relaxed EDC throttling [Disabled] If this option is selected, part-specific EDC throttling protection is enabled. [Enabled] Select this option to reduce the amount of time the processor will throttle. [Auto] AMD's recommendation (Disabled). Zen Common Options RedirectForReturnDis From a workaround for GCC/C000005 issue for XV Core on CZ A0, setting MSRC001_1029 Decode Configuration (DE_CFG) bit 14 [DecfgNoRdrctForReturns] to 1. L2 TLB Associativity 0 - L2 TLB ways [11:8] are fully associative. 1 - =L2 TLB ways [11:8] are 4K-only. Platform first Error Handling Enable/disable PFEH, cloak individual banks, and mask deferred error interrupts from each bank. Core Performance Boost Disable CPB. Enable IBS Enables IBS through MSRC001_1005[42] and disables SpecLockMap through MSRC001_1020[54]. Global C-state Control Controls IO based C-state generation and DF C-states. 81 English

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English
81
Fatal1ty X399 Professional Gaming Series
Custom Pstates5
Custom P-State5 or leave this item to [Auto].
Custom Pstates6
Custom P-State6 or leave this item to [Auto].
Custom Pstates7
Custom P-State7 or leave this item to [Auto].
Relaxed EDC throttling
[Disabled]
If this option is selected, part-specific EDC throttling protection is enabled.
[Enabled]
Select this option to reduce the amount of time the processor will throttle.
[Auto]
AMD's recommendation (Disabled).
Zen Common Options
RedirectForReturnDis
From a workaround for GCC/C000005 issue for XV Core on CZ A0, setting MSRC001_1029
Decode Configuration (DE_CFG) bit 14 [DecfgNoRdrctForReturns] to 1.
L2 TLB Associativity
0 - L2 TLB ways [11:8] are fully associative.
1 - =L2 TLB ways [11:8] are 4K-only.
Platform first Error Handling
Enable/disable PFEH, cloak individual banks, and mask deferred error interrupts from each
bank.
Core Performance Boost
Disable CPB.
Enable IBS
Enables IBS through MSRC001_1005[42] and disables SpecLockMap through
MSRC001_1020[54].
Global C-state Control
Controls IO based C-state generation and DF C-states.