ASRock Fatal1ty X99X Killer/3.1 User Manual - Page 81

RAS to RAS Delay tRRD_L

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Fatal1ty X99X Killer/3.1 Series DRAM Frequency OC Preset If the DRAM frequency is selected, the corresponding DRAM and BCLK frequency for overclocking will be set.Primary Timing CAS# Latency (tCL) he time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay (tRCD) he number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge Time (tRP) he number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) he number of clock cycles required between a bank active command and issuing the precharge command. Command Rate (CR) he delay between when a memory chip is selected and when the irst active command can be issued. Secondary Timing Write Recovery Time (tWR) he amount of delay that must elapse ater the completion of a valid write operation, before an active bank can be precharged. Refresh Cycle Time (tRFC) he number of clocks from a Refresh command until the irst Activate command to the same rank. RAS to RAS Delay (tRRD) he number of clocks between two rows activated in diferent banks of the same rank. RAS to RAS Delay (tRRD_L) he number of clocks between two rows activated in diferent banks of the same rank. 73 English

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English
Fatal1ty X99X Killer/3.1 Series
73
DRAM Frequency OC Preset
If the DRAM frequency is selected, the corresponding DRAM and BCLK frequency for
overclocking will be set.
Primary Timing
CAS# Latency (tCL)
He time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay (tRCD)
He number of clock cycles required between the opening of a row of memory and
accessing columns within it.
Row Precharge Time (tRP)
He number of clock cycles required between the issuing of the precharge command
and opening the next row.
RAS# Active Time (tRAS)
He number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
He delay between when a memory chip is selected and when the ±rst active command can
be issued.
Secondary Timing
Write Recovery Time (tWR)
He amount of delay that must elapse a³er the completion of a valid write operation,
before an active bank can be precharged.
Refresh Cycle Time (tRFC)
He number of clocks from a Refresh command until the ±rst Activate command to
the same rank.
RAS to RAS Delay (tRRD)
He number of clocks between two rows activated in di´erent banks of the same
rank.
RAS to RAS Delay (tRRD_L)
He number of clocks between two rows activated in di´erent banks of the same
rank.