Acer Aspire SA80 Aspire SA80 and Power S280 Service Guide - Page 54

DRAM Clock/Timing Control Phoenix - AwardBIOS CMOS Setup Utilitye DRAM Clock/Timing Control Current CPU Frequency 133 MHz Item Help Current DRAM Frequency 200 MHz DRAM Timing Control [By SPD] Menu Level X x DRAM CAS Latency 2.5T x RAS Active Time (tRAS) 6T x RAS Recharge Time (tRP) 3T x RAS to CAS Delay (tRCD) 3T KLIJ: Move Enter: Select +/-/PU/PD: Value F10:Save ESC: Exit F5: Previous Values F7: Optimized Defaults F1: General Help Parameter Current CPU Frequency Current DRAM Frequency DRAM Timing Control DRAM CAS Latency RAS Active Time (tRAS) RAS Precharge Time (tRP) RAS to CAS Delay (tRCD) Description Detect the current CPU Frequency Detect the current DRAM Frequency Enables you to select the CAS latency time in HCLKs of 2, 2.5, or 3. The value is set at the factory depending on the DRAM installed. Do not change the values in this field unless you change specifications of the installed DRAM or the installed CPU. This item controls the timing delay (in clock cycles) before the DRAM starts a read command after receiving it. This item allows you to set the amount of time a RAS can be kept open for multiple accesses. High figures will improve performance. This is the duration of the time interval during which the Row Address Strobe signal to a DRAM is held low during normal Read and Write Cycles. This is the munimum interval between completing one read or write and starting another from the same (non-page mode) DRAM. Techniques such as memory interleaving, or use of Page Mode DRAM are often used to avoid this delay. Some chipsets require this parameter in order to set up the memory configuration properly. The RAS Precharge value is typically about the same as the RAM Access (data read/write) time. This is the amount of time a CAS is performed after a RAS. This lower the better, but some DRAM does not support low figures. 46 Chapter 2