Acer R310-U-P3200 User Guide - Page 33

Initialize CPU registers., Checkpoint, Beep Code, Description - bios

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23 Checkpoint Code Beep Code 09h 0Ah 0Bh 0Ch 0Eh 0Fh 10h 11h 12h 13h Description Set in-POST flag in CMOS that indicates we are in POST. If this bit is not cleared by postClearBootFlagJ (AEh), the BIOS on next boot determines that the current configuration caused POST to fail and uses default values for configuration. Clear the CMOS diagnostic byte (register E). Check the real-time clock and verify the battery has not lost power. Checksum the CMOS and verify it has not been corrupted. Initialize CPU registers. Enable CPU cache. Set bits in CMOS related to cache. Set the initial POST values of the cache registers if not integrated into the chipset. Set the initial POST values of registers in the integrated I/O chip. Enable the local bus IDE as primary or secondary depending on other drives detected. Initialize power management. General dispatcher for alternate register initialization. Set initial POST values for other hardware devices defined in the register tables. Restore the contents of the CPU control word whenever the CPU is reset. Early reset of PCI devices required to disable bus master. Assumes the presence of a stack and running from decompressed shadow memory.

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23
09h
Set in-POST flag in CMOS that indicates we
are in POST. If this bit is not cleared by post-
ClearBootFlagJ (AEh), the BIOS on next boot
determines that the current configuration
caused POST to fail and uses default values
for configuration.
Clear the CMOS diagnostic byte (register E).
Check the real-time clock and verify the bat-
tery has not lost power. Checksum the
CMOS and verify it has not been corrupted.
0Ah
Initialize CPU registers.
0Bh
Enable CPU cache. Set bits in CMOS related
to cache.
0Ch
Set the initial POST values of the cache reg-
isters if not integrated into the chipset.
0Eh
Set the initial POST values of registers in the
integrated I/O chip.
0Fh
Enable the local bus IDE as primary or
secondary depending on other drives
detected.
10h
Initialize power management.
11h
General dispatcher for alternate register ini-
tialization.
Set initial POST values for other hardware
devices defined in the register tables.
12h
Restore the contents of the CPU control
word whenever the CPU is reset.
13h
Early reset of PCI devices required to disable
bus master. Assumes the presence of a stack
and running from decompressed shadow
memory.
Checkpoint
Code
Beep Code
Description