Acer R310-U-P3200 User Guide - Page 35

Test first 512K of RAM., Initialize the POST Memory Manager. - specifications

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Page 35 highlights

25 Checkpoint Code Beep Code 1Ch 20h 1-3-1-1 22h 1-3-1-3 24h 28h 1-3-3-1 29h 1-3-3-2 2Ah 2Ch 1-3-4-1 2Eh 1-3-4-3 2Fh 32h 33h 34h 1-4-2-1 36h 38h 3Ah Description Initialize interrupt controllers for some shutdowns. Verify that DRAM refresh is operating by polling the refresh bit in PORTB. Reset the keyboard. Set segment-register addressibility to 4 GB. Using the table of configurations supplied by the specific chipset module, test each DRAM configuration to see if that particular configuration is valid. Then program the chipset to its autosized configuration. Before autosizing, disable all caches and all shadow RAM. Initialize the POST Memory Manager. Zero the first 512K of RAM. Test 512K base address lines. Test first 512K of RAM. Initialize external cache before shadowing. Compute CPU speed. Initialize the Phoenix Dispatch Manager. CMOS test. Vector to proper shutdown routine. Shadow the system BIOS. Autosize external cache and program cache size for enabling later in POST.

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25
1Ch
Initialize interrupt controllers for some shut-
downs.
20h
1-3-1-1
Verify that DRAM refresh is operating by
polling the refresh bit in PORTB.
22h
1-3-1-3
Reset the keyboard.
24h
Set segment-register addressibility to 4 GB.
28h
1-3-3-1
Using the table of configurations supplied
by the specific chipset module, test each
DRAM configuration to see if that particular
configuration is valid. Then program the
chipset to its autosized configuration.
Before autosizing, disable all caches and all
shadow RAM.
29h
1-3-3-2
Initialize the POST Memory Manager.
2Ah
Zero the first 512K of RAM.
2Ch
1-3-4-1
Test 512K base address lines.
2Eh
1-3-4-3
Test first 512K of RAM.
2Fh
Initialize external cache before shadowing.
32h
Compute CPU speed.
33h
Initialize the Phoenix Dispatch Manager.
34h
1-4-2-1
CMOS test.
36h
Vector to proper shutdown routine.
38h
Shadow the system BIOS.
3Ah
Autosize external cache and program cache
size for enabling later in POST.
Checkpoint
Code
Beep Code
Description