Asus P5P800 SE P5P800 SE User's Manual for English Edition - Page 82

4.4.3 Chipset The Chipset menu allows you to change the advanced chipset settings. Select an item then press to display the sub-menu. Advanced Chipset Settings WARNING: Setting wrong values in the sections below may cause the system to malfunction. Configure DRAM Timing by SPD Memory Acceleration Mode DRAM Idle Timer DRAM Refresh Rate [Enabled] [Auto] [Auto] [Auto] Graphic Adapter Priority Graphics Aperture Size Spread Spectrum [AGP/PCI] [ 64MB] [Enabled] MPS Revision [1.1] Select Screen Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit Advanced Chipset Settings Configure DRAM Timing by SPD [Enabled] When this item is enabled, the DRAM timing parameters are set according to the DRAM SPD (Serial Presence Detect). When disabled, you can manually set the DRAM timing parameters through the DRAM sub-items. The following sub-items appear when this item is Disabled. Configuration options: [Disabled] [Enabled] DRAM CAS# Latency [2.5 Clocks] Controls the latency between the SDRAM read command and the time the data actually becomes available. Configuration options: [2.0 Clocks] [2.5 Clocks] [3.0 Clocks] DRAM RAS# Precharge [4 Clocks] Controls the idle clocks after issuing a precharge command to the DDR SDRAM. Configuration options: [4 Clocks] [3 Clocks] [2 Clocks] DRAM RAS# to CAS# Delay [4 Clocks] Controls the latency between the DDR SDRAM active command and the read/write command. Configuration options: [4 Clocks] [3 Clocks] [2 Clocks] DRAM RAS# Activate to Precharge Delay [8 Clocks] Sets the RAS Activate to Precharge timing. Configuration options: [8 Clocks] [7 Clocks] [6 Clocks] [5 Clocks] DRAM Burst Length [8 Clocks] Sets the DRAM Burst Length. Configuration options: [4 Clocks] [8 Clocks] 4-22 Chapter 4: BIOS setup