Asus P5VD2 MX P5VD2-MX User's Manual for English Edition - Page 69
CPU L1 & L2 Cache [Enabled], DRAM Clock/Drive Control - vm manual
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CPU L1 & L2 Cache [Enabled] Configuration options: [Disabled] [Enabled] 2.4.2 Chipset Advanced Phoenix-Award BIOS CMOS Setup Utility Chipset DRAM Clock/Drive Control Frequency/Voltage control Top Performance Primary Display Adapter VGA Share Memory Size [Disabled] [PCI-E] [64M] Select Menu Item Specific Help DRAM Clock/Drive Control Advanced Phoenix-Award BIOS CMOS Setup Utility DRAM Clock/Drive Control Current DRAM Frequency DRAM Frequency DRAM Timing Selectable x CAS Latency Time x Bank Interleave x Precharge to Active(Trp) x Active to Precharge(Tras) x Active to CMD(Trcd) x REF to ACT/REF(Trfc) x ACT(0) to ACT(1) (TRRD) 200MHz Auto [By SPD] 4 Disabled 4T 07T 4T 20T/21T 3T Select Menu Item Specific Help DRAM Frequency [Auto] Configuration options: [Auto] [400 MHz] [533 MHz] DRAM Timing Selectable [By SPD] Configuration options: [Manual] [By SPD] The following items are user-configurable when the " D R A M T i m i n g S e l e c t a b l e " item is set to [Manual]. CAS Latency Time [4] Configuration options: [2] [3] [4] [5] Bank Interleave [Disabled] Configuration options: [Disabled] [2 Bank] [4 Bank] [8 Bank] Precharge to Active(Trp) [4T] Configuration options: [2T] [3T] [4T] [5T] ASUS P5VD2-MX/P5V-VM DH 2-21