Gigabyte GA-7TCSV4 Manual - Page 33

Processor Power Management

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2-2-1-1 Processor Power Management EIST (GV3) & C State Conventional Enhanced Intel SpeedStep Technology (EIST) switches both voltage and frequency in tandem between high and low levels in response to processor load. This allows user to configure EIST (GV3) & C State. Options available: Enabled/Disabled. Default setting is Enabled. EIST (GV3) Enable/Disable EIST (GV3). Options available: Enabled/Disabled. Default setting is Enabled. EIST PSD Function In HW_ALL mode, the processor hardware is responsible for coordinating the P-state among logical processors dependencies. The OS is responsible for keeping the P-state request up to date on all logical processors. In SW_ALL mode, the OS Power Manager is responsible for coordinating the P-state among logical processors with dependencies and must initiate the transition on all of those Logical Processors. In SW_ANY mode, the OS Power Manager is responsible for coordinating the P-state among logical processors with dependencies and may initiate the transition on any of those Logical Processors. Options available: HW_ALL/SW_ALL/SW_ANY. Default setting is HW_ALL. Turbo Mode When this feature is enabled, the processor can dynamically overclock one or two of its four processing cores to improve performance with applications that are not multi-threaded or optimized for quad-core processors. Options available: Enabled/Disabled. Default setting is Enabled T State Enable/Disable T State support . - 33 - BIOS Setup

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- 33 -
BIOS Setup
2-2-1-1 Processor Power Management
EIST (GV3) & C State
Conventional Enhanced Intel SpeedStep Technology (EIST) switches both voltage and frequency in
tandem between high
and low levels in response to processor load.
This allows user to
configure EIST (GV3) & C State.
Options available: Enabled/Disabled. Default setting is
Enabled
.
EIST (GV3)
Enable/Disable EIST (GV3).
Options available: Enabled/Disabled. Default setting is
Enabled
.
EIST PSD Function
In HW_ALL mode, the processor hardware is responsible for coordinating the P-state among logical
processors dependencies. The OS is responsible for keeping the P-state request up to date on all
logical processors.
In SW_ALL mode, the OS Power Manager is responsible for coordinating the P-state among logical
processors with dependencies and must initiate the transition on all of those Logical Processors.
In SW_ANY mode, the OS Power Manager is responsible for coordinating the P-state among logical
processors with dependencies and may initiate the transition on any of those Logical Processors.
Options available: HW_ALL/SW_ALL/SW_ANY. Default setting is
HW_ALL
.
Turbo Mode
When this feature is enabled, the processor can dynamically overclock one or two of its four processing
cores to improve performance with applications that are not multi-threaded or optimized for quad-core
processors.
Options available: Enabled/Disabled. Default setting is
Enabled
T State
Enable/Disable T State support .