HP DL165 Technologies for HP ProLiant 100-series G5 (Generation 5) servers, 2n - Page 6

Memory technologies Depending on the model, ProLiant 100-series servers support fully-buffered, unbuffered, and registered PC2-5300 (DDR2) DIMMs as indicated in Table 2. Unbuffered DDR2 DIMMs place the load of all the DDR2 devices on the address bus, so they are typically used in systems with a maximum of four memory slots. Registered and Fully-Buffered (FB) DIMMs are used in systems with more than four memory slots. Registered DDR2 DIMMs place a maximum of two loads per DIMM on the memory bus, regardless of how many DDR2 devices are on each DIMM. The point-to-point FB-DIMM architecture enables the electrical load (and signal integrity) for each channel to remain constant, even as FB-DIMMs are added. Table 2. Memory technologies supported by ProLiant 100-series servers ProLiant server DL185 G5 DL180 G5 DL165 G5 DL160 G5 DL120 G5 ML150 G5 ML115 G5 ML110 G5 Memory Type Registered PC2-5300 (DDR2 667 MHz) Registered PC2-5300 (DDR2 667 MHz) Registered PC2-5300 (DDR2 667 MHz) Fully buffered PC2-5300 (DDR2 667 MHz) Unbuffered PC2-6400 (DDR2 800 MHz) Registered PC2-5300 (DDR2 667 MHz) Unbuffered PC2-6400 (DDR2 800 MHz) Unbuffered PC2-6400 (DDR2 800 MHz) In contrast to the first generation of DDR memory, DDR2 memory devices operate at a lower voltage (1.8V) to further reduce power consumption.3 DDR2 devices also use higher clock frequencies to increase data transfer rates and use on-die termination control to improve signal quality. At 200 MHz (double-clocked to an effective frequency of 400 MHz), DDR2 increases memory bandwidth to 3.2 GB/s. I/O technologies The latest generation of ProLiant 100-series servers feature PCI Express, Serial-Attached SCSI (SAS), and Serial ATA (SATA) I/O technologies. PCI Express allows adding expansion cards with various capabilities to the system. SAS is a serial communication protocol for direct attached storage devices such as SAS and SATA hard drives. PCI Express technology The PCI Express (PCIe) serial interface provides point-to-point connections between the chipset I/O controller hub and I/O devices. Each PCIe serial link consists of one or more dual-simplex lanes. Each lane contains a send pair and a receive pair to transmit data at the signaling rate in both directions simultaneously. PCI Express 1.0 has a signaling rate of 2.5 Gb/s per direction per lane, resulting in an effective maximum bandwidth of 2 Gb/s (250 MB/s) per direction per lane after accounting for 3 For additional information about DDR2 memory technology, refer to the HP technology brief titled "Memory technology evolution: an overview of system memory technologies" at http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf. 6