HP Integrity rx7620 Installation Guide, Seventh Edition - HP Integrity rx7620 - Page 15
PCI-X Board to Cell Board Block Diagram
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Introduction Overview of these high-speed bi-directional rope links for a total aggregate bandwidth of approximately 4 GB/sec. Each LBA acts as a bus bridge, supporting either one or two ropes and capable of driving 33 Mhz or 66 Mhz for PCI cards. The LBAs can also drive at 66 Mhz or 133 Mhz for PCI-X cards. Figure 1-4 PCI-X Board to Cell Board Block Diagram Cell Board Cell Controller (CC) Cell Board Cell Controller (CC) LBA System Backplane LBA System Bus Adapter (SBA) System Bus Adapter (SBA) LBA 1 LBA 2 LBA 4 LBA 6 LBA 14 LBA 12 LBA 10 LBA 8 PCI Slot 8 PCI Slot 7 PCI Slot 6 PCI Slot 5 PCI Slot 4 PCI Slot 3 PCI Slot 2 PCI Slot 1 LBA 1 LBA 2 LBA 4 LBA 6 LBA 14 LBA 12 LBA 10 LBA 8 PCI Slot 8 PCI Slot 7 PCI Slot 6 PCI Slot 5 PCI Slot 4 PCI Slot 3 PCI Slot 2 PCI Slot 1 NOTE PCI-X slots 1-7 are dual rope slots while slot 8 is a single rope slot. A rope is defined as a high speed point to point data bus. The PCI-X backplane is the primary I/O interface for HP Integrity rx7620 Server systems. It provides sixteen 64-bit, hot-plug PCI/PCI-X slots. Fourteen of the slots have dual ropes connected to the LBA chips. The remaining two slots have a single rope connected to each LBA chip. Each of the sixteen slots are capable of 66MHz/33MHz PCI or 133MHz/66MHz PCI-X. All sixteen PCI slots are keyed for 3.3 volt connectors (accepting both Universal and 3.3 V cards). The PCI-X backplane does not provide any 5 volt slots for the I/O cards. See Table 1-1 for more details. The PCI-X backplane is physically one board but behaves like two independent partitions. SBA 0 and its associated LBAs and eight PCI-X slots form one I/0 partition. SBA 1 and its associated LBAs and eight PCI-X slots form the other I/0 partition. One I/O partition can be powered down separately from the other I/O partition. Chapter 1 15
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