HP Vectra VEi8 HP Vectra VEi7, VEi8 & VLi8, Technical Reference Manual (V - Page 12

Core Components and Technologies Chip Sets Features of the Intel 440ZX Chip Processor Local Bus Interface The 440ZX chip monitors each cycle that is initiated by the processor, and forwards those to the PCI bus that are not targeted at the local memory. It translates Processor Local (PL) bus cycles into PCI bus cycles. The chip can support one processor at up to 100MHz Front Side Bus clock frequency. PCI Bus Interface The 82443ZX PCI interface is 3.3V (5V tolerant), 33 MHz and is PCI 2.1 compliant. The maximum PCI burst transfer rate is 132 MB/s. The chip supports advanced snooping for PCI master bursting, and provides a pre-fetch mechanism dedicated for IDE read. The PCI arbiter supports PCI bus arbitration for up to six masters using a rotating priority mechanism. Its hidden arbitration scheme minimizes arbitration overhead. AGP Bus Interface A controller for the AGP (Accelerated Graphics Port) slot is integrated in the 440ZX PAC chip. The PAC chip supports only a synchronous AGP interface, coupling to the host bus frequency. The AGP characteristics are described in detail in "Matrox Millennium G200 AGP Graphics (VEi 8, VLi 8 and VLi 8SF PCs)" on page 26. Main Memory Controller The main memory controller in the 440ZX chip supports two DIMM slots. Each slot can host a 168-pin unbuffered SDRAM module, running at 100MHz, for a total of up to 512 MB of dynamic random access memory (non-ECC SDRAM). The memory bus is 72-bits wide, comprised of 64 bits of data and 8 bits of ECC. However, the 440ZX chip does not support ECC operation. 12