HP rp7440 Site Preparation Guide, Fourth Edition - HP Integrity rx7640 and HP - Page 27

PCI-X/PCIe Slot Boot Paths, Table 1-6 PCI-X/PCIe Slot Types

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to the cell controller chip on cell board 2, and the ASIC on cell location 1 connects to the cell controller chip on cell board 3 through external link cables. Downstream, the ASIC spawns 16 logical 'ropes' that communicate with the core I/O bridge on the system backplane, PCI interface chips, and PCIe interface chips. Each PCI chip produces a single 64-bit PCI-X bus supporting a single PCI or PCI-X add-in card. Each PCIe chip produces a single x8 PCI-Express bus supporting a single PCIe add-in card. The ropes in each I/O partition are distributed as follows: • One PCI-X ASIC is connected to each I/O chip with a single rope capable of peak data rates of 533Mb/s (PCIX-66). • Three PCI-X ASICs are connected to each I/O chip with dual ropes capable of peak data rates of 1.06Gb/s (PCIX-133). • Four PCIe ASICs are connected to each I/O chip with dual fat ropes capable of peak data rates of 2.12Gb/s (PCIe x8). In addition, each I/O chip provides an external single rope connection for the core I/O. Each PCI-Express slot on the PCI-X/PCIe I/O board is controlled by its own ASIC and is also independently supported by its own half of the dual hot swap controller. All PCIe slots are designed to be compliant with PCIe Rev.1.0. The PCI-Express I/O backplane will provide slot support for VAUX3.3, SMB*, and JTAG. PCI-X/PCIe Slot Boot Paths PCI-X/PCIe slot boot paths are directly leveraged from the PCI-X backplane. See Table 1-3 (page 24) and Table 1-4 (page 25) for more details. NOTE: The differences between the PCI X backplane and the PCI-X/PCIe backplane are as follows: • Twelve ropes are bundled in two rope pairs to 6 LBAs to support 6 slots for PCI and PCI-X cards instead of 14. These ropes are capable of 133MHz. • Sixteen ropes are bundled into dual fat ropes to 8 LBAs to support 8 additional slots for PCIe cards. These ropes are capable of 266MHz. Table 1-6 PCI-X/PCIe Slot Types I/O Partition 0 Slot1 82 7 6 5 4 3 2 1 Maximum Peak Maximum MHz Bandwidth Ropes 66 533 MB/s 001 133 1.06 GB/s 002/003 266 2.13 GB/s 004/005 266 2.13 GB/s 006/007 266 2.13 GB/s 014/015 266 2.13 GB/s 012/013 133 1.06 GB/s 010/011 133 1.06 GB/s 008/009 Supported Cards 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V PCI Mode Supported PCI or PCI-X Mode 1 PCI or PCI-X Mode 1 PCI-e PCI-e PCI-e PCI-e PCI or PCI-X Mode 1 PCI or PCI-X Mode 1 Detailed Server Description 27

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to the cell controller chip on cell board 2, and the ASIC on cell location 1 connects to the cell
controller chip on cell board 3 through external link cables.
Downstream, the ASIC spawns 16 logical 'ropes' that communicate with the core I/O bridge on
the system backplane, PCI interface chips, and PCIe interface chips. Each PCI chip produces a
single 64–bit PCI-X bus supporting a single PCI or PCI-X add-in card. Each PCIe chip produces
a single x8 PCI-Express bus supporting a single PCIe add-in card.
The ropes in each I/O partition are distributed as follows:
•
One PCI-X ASIC is connected to each I/O chip with a single rope capable of peak data rates
of 533Mb/s (PCIX-66).
•
Three PCI-X ASICs are connected to each I/O chip with dual ropes capable of peak data
rates of 1.06Gb/s (PCIX-133).
•
Four PCIe ASICs are connected to each I/O chip with dual fat ropes capable of peak data
rates of 2.12Gb/s (PCIe x8).
In addition, each I/O chip provides an external single rope connection for the core I/O.
Each PCI-Express slot on the PCI-X/PCIe I/O board is controlled by its own ASIC and is also
independently supported by its own half of the dual hot swap controller. All PCIe slots are
designed to be compliant with PCIe Rev.1.0. The PCI-Express I/O backplane will provide slot
support for VAUX3.3, SMB*, and JTAG.
PCI-X/PCIe Slot Boot Paths
PCI-X/PCIe slot boot paths are directly leveraged from the PCI-X backplane. See
Table 1-3
(page 24)
and
Table 1-4 (page 25)
for more details.
NOTE:
The differences between the PCI X backplane and the PCI-X/PCIe backplane are as
follows:
•
Twelve ropes are bundled in two rope pairs to 6 LBAs to support 6 slots for PCI and PCI-X
cards instead of 14. These ropes are capable of 133MHz.
•
Sixteen ropes are bundled into dual fat ropes to 8 LBAs to support 8 additional slots for
PCIe cards. These ropes are capable of 266MHz.
Table 1-6 PCI-X/PCIe Slot Types
PCI Mode
Supported
Supported
Cards
Ropes
Maximum Peak
Bandwidth
Maximum MHz
Slot
1
I/O Partition
PCI or PCI-X
Mode 1
3.3 V
001
533 MB/s
66
8
2
0
PCI or PCI-X
Mode 1
3.3 V
002/003
1.06 GB/s
133
7
PCI-e
3.3 V
004/005
2.13 GB/s
266
6
PCI-e
3.3 V
006/007
2.13 GB/s
266
5
PCI-e
3.3 V
014/015
2.13 GB/s
266
4
PCI-e
3.3 V
012/013
2.13 GB/s
266
3
PCI or PCI-X
Mode 1
3.3 V
010/011
1.06 GB/s
133
2
PCI or PCI-X
Mode 1
3.3 V
008/009
1.06 GB/s
133
1
Detailed Server Description
27