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Hitachi 7K250 Specifications - Page 64

Read DRQ interval time

UPC - 000004558972

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7.6.2 Read DRQ interval time For read sectors and read multiple operations the interval from the end of negation of the DRQ bit until setting of the next DRQ bit is as follows: • In the event that a host reads the status register only before the sector or block transfer DRQ interval, the DRQ interval 4.2 µs • In the event that a host reads the status register after or both before and after the sector or block transfer, the DRQ interval is 11.5 µs Deskstar 7K250 Hard Disk Drive Specification 50

Section	Page
1.0 General	15
1.1 Introduction	15
1.2 References	15
1.3 Abbreviations	15
1.4 Caution	17
2.0 General features of the drive	19
3.0 Fixed-disk subsystem description	23
3.1 Control electronics	23
3.2 Head disk assembly	23
3.3 Actuator	23
4.0 Drive characteristics	25
4.1 Default logical drive parameters	25
4.2 Data sheet	26
4.3 Drive organization	27
4.3.1 Drive format	27
4.3.2 Cylinder allocation	27
4.4 Performance characteristics	29
4.4.1 Command overhead	29
4.4.2 Mechanical positioning	29
4.4.3 Drive ready time	31
4.4.4 Data transfer speed	32
4.4.5 Throughput	33
4.4.6 Operating modes	34
5.0 Defect flagging strategy	35
6.0 Specification	37
6.1 Jumper settings	37
6.1.1 Jumper pin location	37
6.1.2 Jumper pin identification	37
6.1.3 Jumper pin assignment	38
6.1.4 Jumper positions	38
6.2 Environment	42
6.2.1 Temperature and humidity	42
6.2.2 Corrosion test	43
6.3 DC power requirements	43
6.3.1 Input voltage	43
6.3.2 Power supply current (typical)	43
6.3.3 Power supply generated ripple at drive power connector	45
6.4 Reliability	46
6.4.1 Data integrity	46
6.4.2 Cable noise interference	46
6.4.3 Start/stop cycles	46
6.4.4 Preventive maintenance	46
6.4.5 Data reliability	46
6.4.6 Required power-off sequence	46
6.5 Mechanical specifications	47
6.5.1 Physical dimensions and weight	47
6.5.2 Mounting hole locations	48
6.5.3 Connector locations	49
6.5.4 Drive mounting	49
6.5.5 Heads unload and actuator lock	49
6.6 Vibration and shock	50
6.6.1 Operating vibration	50
6.6.2 Nonoperating vibration	50
6.6.3 Operating shock	51
6.6.4 Nonoperating shock	51
6.6.5 Nonoperating rotational shock	52
6.7 Acoustics	53
6.8 Identification labels	53
6.9 Safety	54
6.9.1 UL and CSA approval	54
6.9.2 German safety mark	54
6.9.3 Flammability	54
6.9.4 Safe handling	54
6.9.5 Environment	54
6.9.6 Secondary circuit protection	54
6.10 Electromagnetic compatibility	55
6.10.1 CE mark	55
6.10.2 C-TICK mark	55
6.10.3 BSMI mark	55
6.11 Packaging	55
7.0 Electrical interface specification	57
7.1 Connector location	57
7.1.1 DC power connector	57
7.1.2 AT signal connector	57
7.2 Signal definitions	58
7.3 Signal descriptions	59
7.4 Interface logic signal levels	62
7.5 Reset timings	62
7.6 PIO timings	63
7.6.1 Write DRQ interval time	63
7.6.2 Read DRQ interval time	64
7.7 Multi word DMA timings	65
7.8 Ultra DMA timings	66
7.8.1 Initiating Read DMA	66
7.8.2 Host Pausing Read DMA	67
7.8.3 Host Terminating Read DMA	68
7.8.4 Device Terminating Read DMA	69
7.8.5 Initiating Write DMA	70
7.8.6 Device Pausing Write DMA	71
7.8.7 Device Terminating Write DMA	72
7.8.8 Host Terminating Write DMA	73
7.9 Addressing of registers	74
7.9.1 Cabling	74
8.0 General	77
8.1 Introduction	77
8.2 Terminology	77
8.3 Deviations from standard	77
9.0 Registers	79
9.1 Register set	79
9.2 Alternate Status Register	80
9.3 Command Register	80
9.4 Cylinder High Register	80
9.5 Cylinder Low Register	80
9.6 Data Register	81
9.7 Device Control Register	81
9.8 Drive Address Register	82
9.9 Device/Head Register	82
9.10 Error Register	83
9.11 Features Register	83
9.12 Sector Count Register	83
9.13 Sector Number Register	84
9.14 Status Register	84
10.0 General operation	87
10.1 Reset response	87
10.2 Register initialization	88
10.3 Diagnostic and Reset considerations	89
10.4 Sector Addressing Mode	90
10.4.1 Logical CHS addressing mode	90
10.4.2 LBA addressing mode	90
10.5 Overlapped and queued feature	90
10.6 Power management features	92
10.6.1 Power mode	92
10.6.2 Power management commands	92
10.6.3 Standby timer	92
10.6.4 Interface capability for power modes	93
10.7 S.M.A.R.T. Function	94
10.7.1 Attributes	94
10.7.2 Attribute values	94
10.7.3 Attribute thresholds	94
10.7.4 Threshold exceeded condition	94
10.7.5 S.M.A.R.T. commands	94
10.7.6 Off-line read scanning	94
10.7.7 Error log	95
10.7.8 Self-test	95
10.8 Security Mode Feature Set	96
10.8.1 Security mode	96
10.8.2 Security level	96
10.8.3 Passwords	97
10.8.4 Operation example	97
10.8.5 Command table	100
10.9 Host Protected Area Feature	101
10.9.1 Example for operation (In LBA Mode)	101
10.9.2 Security extensions	102
10.10 Seek overlap	103
10.11 Write cache function	104
10.12 Reassign function	105
10.12.1 Auto Reassign function	105
10.13 Power-Up in Standby feature set	106
10.14 Advanced Power Management feature set (APM)	107
10.15 Automatic Acoustic Management feature set (AAM)	108
10.16 Address Offset Feature	109
10.16.1 Enable/Disable Address Offset Mode	109
10.16.2 Identify Device Data	110
10.16.3 Exceptions in Address Offset Mode	110
10.17 48-bit Address Feature Set	111
11.0 Command protocol	113
11.1 PIO Data In commands	113
11.2 PIO Data Out Commands	114
11.3 Non-data commands	116
11.4 DMA commands	117
11.5 DMA queued commands	118
12.0 Command descriptions	119
12.1 Check Power Mode (E5h/98h)	123
12.2 Device Configuration Overlay (B1h)	124
12.2.1 DEVICE CONFIGURATION RESTORE	124
12.2.2 DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h)	124
12.2.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h)	125
12.2.4 DEVICE CONFIGURATION SET (subcommand C3h)	125
12.3 Execute Device Diagnostic (90h)	128
12.4 Flush Cache (E7h)	129
12.5 Flush Cache Ext (EAh)	130
12.6 Format Track (50h)	131
12.7 Format Unit (F7h)	132
12.8 Identify Device (ECh)	133
12.9 Idle (E3h/97h)	141
12.10 Idle Immediate (E1h/95h)	142
12.11 Initialize Device Parameters (91h)	143
12.12 NOP (00h)	144
12.13 Read Buffer (E4h)	145
12.14 Read DMA (C8h/C9h)	146
12.15 Read DMA Ext (25h)	148
12.16 Read DMA Queued (C7h)	150
12.17 Read DMA Queued Ext (26h)	152
12.18 Read Log Ext (2Fh)	154
12.18.1 General Purpose Log Directory	155
12.18.2 Extended Comprehensive SMART Error Log	156
12.18.3 Extended Self-test log sector	158
12.19 Read Long (22h/23h)	160
12.20 Read Multiple (C4h)	162
12.21 Read Multiple Ext (29h)	164
12.22 Read Native Max ADDRESS (F8h)	166
12.23 Read Native Max Address Ext (27h)	167
12.24 Read Sectors (20h/21h)	168
12.25 Read Sector(s) Ext (24h)	170
12.26 Read Verify Sectors (40h/41h)	172
12.27 Read Verify Sector(s) (42h)	174
12.28 Recalibrate (1xh)	176
12.29 Security Disable Password (F6h)	177
12.30 Security Disable Password (F3h)	178
12.31 Security Erase Unit (F4h)	179
12.32 Security Freeze Lock (F5h)	181
12.33 Security Set Password (F1h)	182
12.34 Security Unlock (F2h)	184
12.35 Seek (7xh)	185
12.36 Service (A2h )	186
12.37 Set Features (EFh)	187
12.37.1 Set Transfer mode	188
12.37.2 Write Cache	188
12.37.3 Advanced Power Management	188
12.37.4 Automatic Acoustic Management	189
12.38 Set Max ADDRESS (F9h)	190
12.38.1 Set Max Set Password (Feature=01h)	192
12.38.2 Set Max Lock (Feature=02h)	193
12.38.3 Set Max Unlock (Feature = 03h)	194
12.38.4 Set Max Freeze Lock (Feature = 04h)	195
12.39 Set Max Address Ext (37h)	196
12.40 Set Multiple (C9h)	198
12.41 Sleep (E6h/99h)	199
12.42 S.M.A.R.T. Function Set (B0h)	200
12.42.1 S.M.A.R.T. Function Subcommands	200
12.42.2 Device Attribute Data Structure	204
12.42.3 Device Attribute Thresholds data structure	207
12.42.4 S.M.A.R.T. Log Directory	209
12.42.5 S.M.A.R.T. summary error log sector	209
12.42.6 Self-test log data structure	211
12.42.7 Error reporting	212
12.43 Standby (E2h/96h)	213
12.44 Standby Immediate (E0h/94h)	214
12.45 Write Buffer (E8h)	215
12.46 Write DMA (CAh/CBh)	216
12.47 Write DMA Ext (35h)	218
12.48 Write DMA Queued (CAh/CBh)	220
12.49 Write DMA Queued Ext (36h)	222
12.50 Write Log Ext (3Fh)	224
12.51 Write Long (32h/33h)	225
12.52 Write Multiple (C5h)	227
12.53 Write Multiple Ext (39h)	229
12.54 Write Sectors (30h/31h)	231
12.55 Write Sector(s) (34h)	233