Intel BLKD865PERL Product Specification - Page 54
Fixed I/O Map
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Intel Desktop Board D865PERL Technical Product Specification 2.4 Fixed I/O Map Table 15. I/O Map Address (hex) Size Description 0000 - 00FF 256 bytes Used by the Desktop Board D865PERL. Refer to the ICH5 data sheet for dynamic addressing information 0170 - 0177 8 bytes Secondary Parallel ATA IDE channel command block 01F0 - 01F7 8 bytes Primary Parallel ATA IDE channel command block 0228 - 022F (Note 1) 0278 - 027F (Note 1) 02E8 - 02EF (Note 1) 02F8 - 02FF (Note 1) 8 bytes 8 bytes 8 bytes 8 bytes LPT3 LPT2 COM4 COM2 0374 - 0377 0378 - 037F 03B0 - 03BB 03C0 - 03DF 03E8 - 03EF 03F0 - 03F5 03F4 - 03F7 4 bytes 8 bytes 12 bytes 32 bytes 8 bytes 6 bytes 4 bytes Secondary Parallel ATA IDE channel control block LPT1 Intel 82865PE MCH Intel 82865PE MCH COM3 Diskette channel Primary Parallel ATA IDE channel control block 03F8 - 03FF 8 bytes COM1 04D0 - 04D1 2 bytes Edge/level triggered PIC LPTn + 400 0CF8 - 0CFB (Note 2) 0CF9 (Note 3) 0CFC - 0CFF FFA0 - FFA7 FFA8 - FFAF 8 bytes 4 bytes 1 byte 4 bytes 8 bytes 8 bytes ECP port, LPTn base address + 400h PCI configuration address register Reset control register PCI configuration data register Primary Parallel ATA IDE bus master registers Secondary Parallel ATA IDE bus master registers Notes: 1. Default, but can be changed to another address range 2. Dword access only 3. Byte access only For information about ICH5 addressing Refer to Section 1.2, page 16 54