Intel D845EPI Intel Desktop Board D845EPI Technical Product Specification - Page 89

Table 55., Chipset Configuration Submenu

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BIOS Setup Program Table 55. Chipset Configuration Submenu (continued) Feature SDRAM Timing Control Options • Auto (default) • Manual - Aggressive • Manual - User Defined SDRAM RAS# Active to • 7 Precharge • 6 • 5 (default) SDRAM CAS# Latency • 2.0 (default) • 2.5 SDRAM RAS# to CAS# • 3 Delay • 2 (default) SDRAM RAS# Precharge • 3 • 2 (default) Description Auto = Timings will be programmed according to the memory detected. Manual - Aggressive = Selects most aggressive user-defined timings. Manual - User Defined = Allows manual override of detected SDRAM settings. Corresponds to tRAS. Selects the number of clock cycles required to address a column in memory. Selects the number of clock cycles between addressing a row and addressing a column. Selects the length of time required before accessing a new row. 89

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BIOS Setup Program
89
Table 55.
Chipset Configuration Submenu
(continued)
Feature
Options
Description
SDRAM Timing Control
•
Auto (default)
•
Manual
–
Aggressive
•
Manual
–
User Defined
Auto
= Timings will be programmed according to the
memory detected.
Manual –
Aggressive
= Selects most aggressive
user-defined timings.
Manual
–
User Defined
= Allows manual override of
detected SDRAM settings.
SDRAM RAS# Active to
Precharge
•
7
•
6
•
5 (default)
Corresponds to tRAS.
SDRAM CAS# Latency
•
2.0 (default)
•
2.5
Selects the number of clock cycles required to
address a column in memory.
SDRAM RAS# to CAS#
Delay
•
3
•
2 (default)
Selects the number of clock cycles between
addressing a row and addressing a column.
SDRAM RAS#
Precharge
•
3
•
2 (default)
Selects the length of time required before accessing
a new row.