Intel E3300 Data Sheet - Page 85

Features 6 Features 6.1 Table 28. Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 28. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for configuration purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset. Power-On Configuration Option Signals Configuration Option Signal1,2 Output tristate Execute BIST Disable dynamic bus parking Symmetric agent arbitration ID RESERVED SMI# A3# A25# BR0# A[24:4]#, A[35:26]# NOTE: 1. Asserting this signal during RESET# will select the corresponding option. 2. Address signals not identified in this table as configuration options should not be asserted during RESET#. 3. Disabling of any of the cores within the processors must be handled by configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core per die within the processor package. 6.2 Clock Control and Low Power States The processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 17 for a visual representation of the processor low power states. Datasheet 85