Intel S3000PT Product Specification - Page 21

Intel® Server Board S3000PT TPS Functional Architecture The third/fourth USB port is optional and can be accessed by cabling from an internal 9 -pin connector located on the server board to an external USB port located either in front of or on the rear of a given chassis. 3.2.2.2.3 Enhanced Power Management The Intel® ICH7R controller's power management functions include enhanced clock control and various low-power (suspend) states (e.g., Suspend -to-RAM and Suspend-to-Disk). A hardwarebased thermal management circuit permits a software-independent entrance to low-power states. The Intel® ICH7R controller contains full support for the Advanced Configuration and Power Interface (ACPI) Specification, Revision 3.0. The server board supports sleep states S1, S4, and S5. 3.3 Memory Sub-System The memory interface between the MCH and the DIMMs is a 72-bit (ECC) wide interface. There are two banks of DIMMs, labeled 1 and 2. Bank 1 contains DIMM socket locations DIMM_1A and DIMM_1B. Bank 2 contains DIMM socket locations DIMM _2A and DIMM_2B. The sockets associated with each bank , or "channel," are located next to each other, and the DIMM socket identifiers are marked on the base board silkscreen, near the DIMM socket. When only two DIMM modules are being used, the population order must be DIMM_1A, DIMM_1B to ensure dual-channel operating mode. In order to operate in dual-channel dynamic paging mode, the following conditions must be met:  Two identical DIMMs are installed, one each in DIMM_1A and DIMM_1B  Four identical DIMMs are installed (one in each socket location) Note: Installing only three DIMMs is not supported . Do not use DIMMs that are not "matched" (same type and speed). Use of identical memory parts is always the preferred method. See Figure 3 for reference. The system design is free to populate or not to populate any rank on either channel, including either degenerate single channel case. Revision 1.3 13