Intel S3210SHLX Product Specification - Page 90

Error Reporting and Handling Intel® Server Boards S3200SH/S3210SH TPS 5. Error Reporting and Handling This chapter defines following error handling features: • Error Handling and Logging • Error Messages and Beep Codes 5.1 Error Handling and Logging This section defines how errors are handled by the system BIOS. In addition, error-logging techniques are described and beep codes for errors are defined. 5.1.1 Error Sources and Types One of the major requirements of server management is to correctly and consistently handle system errors. System errors that can be enabled and disabled individually or as a group can be categorized as follows: • PCI bus • Memory single- and multi-bit errors • Errors detected during POST, logged as POST errors The event list follows: Event Name Processor thermal trip of last boot Memory channel A Multi-bit ECC error Memory channel A Single-bit ECC error Memory channel B Multi-bit ECC error Memory channel B Single-bit ECC error CMOS battery failure CMOS checksum error CMOS time not set Keyboard not found Memory size decrease Chassis intrusion detected Bad SPD tolerance Table 41. Event List Description Processor thermal trip happened on last boot. Multi-bit ECC error happened on DIMM channel A. Single-bit ECC error happened on DIMM channel A. Multi-bit ECC error happened on DIMM channel B. Single-bit ECC error happened on DIMM channel B. CMOS battery failure or CMOS clear jumper is set to clear CMOS. CMOS data crushed CMOS time is not set PS/2 KB is not found during POST Memory size is decreased compared with last boot Chassis is open Some fields of the DIMM SPD may not be supported, but could be tolerant by the Memory Reference When Error Is Caught POST POST / Runtime POST / Runtime POST / Runtime POST / Runtime POST POST POST POST POST POST POST 76 Revision 1.3