MSI 990XA User Guide - Page 49

Chapter 3 MS-7640 ▶ tRC The row cycle time determines the minimum number of clock cycles a memory row takes to complete a full cycle, from row activation up to the precharging of the active row. ▶ tWR Minimum time interval between end of write data burst and the start of a precharge command. Allows sense amplifiers to restore data to cells. ▶ tRRD Specifies the active-to-active delay of different banks. ▶ tWTR Minimum time interval between the end of write data burst and the start of a columnread command. It allows I/O gating to overdrive sense amplifiers before read command starts. ▶ tRFC This setting determines the time RFC takes to read from and write to a memory cell. ▶ Advanced Channel 1/ 2 Timing Configuration Press to enter the sub-menu. And you can set the advanced memory timing for each channel. ▶ tRWTT02/ tWRRD2/ tWRWR2/ tRDRD2 These items is used to set the memory timings for memory channel 1/ 2. ▶ DCT Unganged Mode This feature is used to Integrate two 64-bit DCTs into a 128-bit interface. ▶ Bank Interleaving Bank Interleaving is an important parameter for improving overclocking capability of memory. It allows system to access multiple banks simultaneously. ▶ HT Link Speed This item allows you to set the Hyper-Transport Link speed. Setting to [Auto], the system will detect the HT link speed automatically. ▶ Adjusted HT Link Frequency It shows the adjusted HT Link frequency. Read-only. ▶ CPU Core Control This item allows you to select the number of active processor cores. ▶ Unlock CPU Core This item is used to unlock the CPU core. Please refer to the procedures below for CPU core unlocked in BIOS setup. 3-13