Samsung ML-1440 Service Manual - Page 7

Block Diagram

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Repair Manual 1-1 Sys Cntl BUS Sys Data BUS Sys Addr BUS CPU DATA BUS CPU Addr BUS Samsung Electronics OSC. 20 M H z POWER ON RESET PLL Reset & W D T Generation RCS ROM/SRAM/ FLASH ROM RD Control WR (4 Bank) IOCS I/O Control (5 Bank) OSC.(Video) 53.0109277MHz GPIO Interrupt Control (4 External) Timer (3 CH) Tone Generator VIS Engine Comm. I/F RAM : 512B AD C SPGPe (KS32C61100) ARM 7TDM I Cache 8 KB PROGRAM ROM (FLASHMEMORY) 512K*16b*2EA FONT ROM (MASK ROM) 512K*16b*2EA DATA ROM (DRAM) 1M*16b*2EA SIMM (Up to 64MB) (Option) Post Script 3 (Flash : 2MB Font : 2MB) (Option) A/D Bus CPU B us In te rf ace Blo ck S yste rm Bu s I nt erfa ce B loc k [A rbite r] UA RT ( 3 CH) JB IG LR AM :1296B C XRAM :256B /CS,/RD ,/W R EDO / FPM DRAM Control (4Bank) MA MD RAS CAS G E U P V C P P I D M A C (2 CH) HCT HPVC RAM 512B + 512B OSC. 48 MHz USB INTERFACE IC (USBN9602) CPU DATA BUS CPU ADDR. BUS SYSTEM DATA BUS SYSTEM ADDR. BUS NETWORK INTERFACE (Option) PARALLEL INTERFACE USB INTERFACE I /O INTERFACE 74HC245*2EA 74LS273*3EA PANEL INTERCACE MOTOR CONTROL NV RAM INTERCACE SENSORS INPUT SOLENOID CONTROL FAN/PTL CONTROL LSU INTERFACE HVPS CONTROL FUSER CONTROL SCF INTERFACE [ LASER DIODE ON/OFF SWITCH ] Laser Diode Vcc on LSU THERM STOR ADC INPUT THV READ ADC INPUT SUPPLY 5V to each ICS 5V SMPS 24V SUPPLY 24V to Motor/HVPS/FAN/LSUA 24VS [ COVER OPEN SWITCH ] 11. Block Diagram BLOCK DIAGRAM

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1
1-1
Samsung Electronics
BLOCK DIAGRAM
Repair Manual
1. Block Diagram
OSC.
48 MHz
USB
INTERFACE IC
(USBN9602)
USB
INTERFACE
PARALLEL
INTERFACE
SPGPe
(KS32C61100)
OSC.
20MHz
POWER
ON RESET
PROGRAM ROM
(FLASHMEMORY)
512K*16b*2EA
FONT ROM
(MASK ROM)
512K*16b*2EA
DATA ROM
(DRAM)
1M*16b*2EA
SIMM
(Up to 64MB)
(Option)
Post Script 3
(Flash
:
2MB
Font
:
2MB)
(Option)
RAS
CAS
MA
MD
RCS
RD
WR
IOCS
PLL
Reset
&
W D T
Generation
ROM/SRAM/
FLASH
ROM
Control
(4 Bank)
I/O
Control
(5 Bank)
Interrupt
Control
(4 External)
Timer
(3 CH)
Tone
Generator
Engine
Comm. I/F
RAM : 512B
GPIO
VIS
CPU Bus
In te rf ace
Block
Systerm Bus
Interface
Block
[Arbiter]
EDO / FPM
DRAM
Control
(4Bank)
A/D Bus
CPU
Addr
BUS
CPU
DATA
BUS
Sys Addr BUS
Sys
Data BUS
Sys
Cntl BUS
ARM 7TDMI
Cache
8KB
ADC
U A RT
( 3 CH )
JBIG
RAM
512B
+
512B
OSC.(Video)
53.0109277MHz
/CS,/RD,/WR
NETWORK
INTERFACE
(Option)
SYSTEM
DATA
BUS
SYSTEM
ADDR.
BUS
CPU
DATA
BUS
CPU
ADDR.
BUS
I
/ O
INTERFACE
74HC245*2EA
74LS273*3EA
THERM
STOR
ADC
INPUT
THV
READ
ADC
INPUT
[ COVER OPEN SWITCH ]
[ LASER DIODE ON/OFF SWITCH ]
SMPS
SUPPLY
5V
to
each
ICS
24V
5V
24VS
SUPPLY
24V to
Motor/HVPS/FAN/LSUA
Laser
Diode
Vcc
on
LSU
LRAM
:1296B
CXRAM
:256B
PANEL INTERCACE
MOTOR
CONTROL
NV RAM INTERCACE
SENSORS
INPUT
SOLENOID CONTROL
FAN/PTL CONTROL
SCF INTERFACE
FUSER CONTROL
HVPS
CONTROL
LSU
INTERFACE
G E U
P V C
P P I
HPVC
HCT
D M A C
(2 CH)