Toshiba R600-SP2801C Maintenance Manual - Page 70
Initialization of ICH APIC
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2 Troubleshooting Procedures 2.4 System Board Troubleshooting Table 2-5 Debug port error status (2/8) System BIOS IRT processing Debug BIOS processing Code Target Device IC No. F100 F101 F102 CPU setup Initialization of ICH, MCH, and Super I/O setup of SD controller setup of PIT Memory initialization Memory error setup for using RAM area check memory error of RAM area memory error CPU ICH(PCIRegister,PITContro ller) MCH(PCIRegister) SDController BIOSROM IC1050(CPU) IC1600(ICH) IC1200(MCH) IC2000(SDController) IC3001(BIOS ROM) MCH(PCIRegister) RAM(SPD,Memory) ICH(PCIRegister,CMOS) CPU BIOSROM IC1200(MCH) IC1420,1421,1430,1431(RAM ) IC1440,1441,1450,1451(RAM ) CN1410(RAM Conn.) IC1600(ICH) IC1050(CPU) IC3001(BIOS ROM) F103 F104 CPU setup CMOS setup CMOS error Resume branch BIOS processing reading ROM read error CPU ICH(CMOS) BIOSROM ICH(CMOS) BIOSROM RAM IC1050(CPU) IC1600(ICH) IC3001(BIOS ROM) IC1200(MCH) IC3001(BIOS ROM) IC1420,1421,1430,1431(RAM ) IC1440,1441,1450,1451(RAM ) CN1410(RAM Conn.) F105 check of BIOS processing EC/KBC(EC) TPM CPU IC3200(EC/KBC) IC3300(TPM) IC1050(CPU) RAM setup F106 Initialization of ICH (APIC) CPU ICH(CMOS,PICController,I /O,MEM I/O) RAM IC1050(CPU) IC1600(ICH) IC1420,1421,1430,1431(RAM ) IC1440,1441,1450,1451(RAM ) CN1410(RAM Conn.) F107 Initialization of ICH (PIT) PIT initialization error CPU check check of ROM data SMI setup Part number data distinction Panel distinction CMOS check Clock generator setup CPU initialization CPU ICH(PITController,MEM I/O,CMOS,I/O) Clock Generator IC1050(CPU) IC1600(ICH) IC1000(Clock Generator) 2-24 [CONFIDENTIAL] PORTEGE R600 Maintenance Manual (960-709)