Via EPIA-5000 User Manual - Page 43
DRAM Clock/Drive Control, DRAM Clock, DRAM Timing By SPD, SDRAM Cycle Length, Bank Interleave
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Chapter 3 DRAM Clock/Drive Control Press to enter the sub-menu and the following screen appears: DRAM Clock Set the DRAM Clock. Settings: Host CLK, HCLK-33M and By Auto. DRAM Timing By SPD Set DRAM Timing by SPD. Settings: Disabled and Enabled. SDRAM Cycle Length Set the SDRAM Cycle Length. Settings: 3 and 2. Bank Interleave Set the Bank Interleave mode. Settings: Disabled, 2 Bank and 4 Bank. 3-12
Chapter 3
3-12
DRAM Clock/Drive Control
Press <Enter> to enter the sub-menu and the following screen appears:
DRAM Clock
Set the DRAM Clock. Settings:
Host CLK
,
HCLK-33M
and
By Auto
.
DRAM Timing By SPD
Set DRAM Timing by SPD. Settings:
Disabled
and
Enabled.
SDRAM Cycle Length
Set the SDRAM Cycle Length. Settings:
3
and
2.
Bank Interleave
Set the Bank Interleave mode. Settings:
Disabled,
2 Bank
and
4
Bank.