ViewSonic VG150B Service Manual - Page 27

Functional, Descriptions

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Service Manual VG150 THEORY OF CIRCUIT OPERATION ViewSonic April 1999 - Version 1.0 The MTV112E micro controller is an 8051CPU core embedded device specially tailored to CRT monitor applications. It includes an 8051 CPU core, 256 bytes SRAM, fourteen built-in PWM DACs, DDC1/DDC2B interface, 24Cxx series EEPROM interface, ND converter and a 32K bytes internal program EPROM. < > P1.0-7 P0.0-7 RD P0.0-7 RD XFR X1 WR ► WR 8051 CORE INT1 WATCH-DOG < > P2.0-3 4 RST TIMER RST P3.0-P3.2 P3.4 P2.4-7 V HSCL HSDA DDC 1/2 B & FIFO INTERFACE HSYNC HNSYNC VSYNC 4 0 CONTROL HBLANK VBLANK 14 CHANNEL DA0-B PWM DAC DA10-13 • IIC INTERFACE ISCL ISDA FUNCTIONAL DESCRIPTIONS 8051 CPU Core 1. The M11/112E includes all the 8051 functions with the following exceptions, PSEN, ALE, RD and WR pins are disabled. The external RAM access is restricted to XFRs within the MTV112E. 2. Porto, port3.3, and port3.5 port3.7 are not general-purpose I/O ports. They are dedicated to monitor control or DAC pins. 3. INT1 and T1 input pins are not provided. 4. Port2.4 port2.7 are shared with DAC pins; port3.0 port3.2 port3.4 are shared with monitor control pins. In addition, there are 2 timers, 5 interrupt sources and serial interface compatible with the standard 8051. The Txd/Rxd (P3./P3.1) pins are shared with DDC interface. INTO/TO pins are shared with IIC interface. An extra option can be used to switch the INTO source from P3.2 to P2.0. This feature maintains an external interrupt source when IIC interface Page 24

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Service
Manual
VG150
ViewSonic
April
1999
-
Version
1.0
THEORY
OF
CIRCUIT
OPERATION
The
MTV112E
micro
controller
is
an
8051CPU
core
embedded
device
specially
tailored
to
CRT
monitor
applications.
It
includes
an
8051
CPU
core,
256
bytes
SRAM,
fourteen
built-in
PWM
DACs,
DDC1/DDC2B
interface,
24Cxx
series
EEPROM
interface,
ND
converter
and
a
32K
bytes
internal
program
EPROM.
<
>
<
>
P1.0-7
X1
8051
CORE
P0.0-7
RD
WR
INT1
P2.0-3
RST
P3.0
-P3.2
P3.4
P2.4-7
►
P0.0-7
RD
XFR
WR
4
WATCH
-DOG
TIMER
RST
V
HSCL
HSDA
DDC
1/2
B
&
FIFO
INTERFACE
FUNCTIONAL
DESCRIPTIONS
8051
CPU
Core
HNSYNC
HSYNC
VSYNC
4
0
CONTROL
HBLANK
VBLANK
14
CHANNEL
DA0-B
PWM
DAC
DA10-13
•
ISCL
IIC
INTERFACE
ISDA
1.
The
M11/112E
includes
all
the
8051
functions
with
the
following
exceptions,
PSEN,
ALE,
RD
and
WR
pins
are
disabled.
The
external
RAM
access
is
restricted
to
XFRs
within
the
MTV112E.
2.
Porto,
port3.3,
and
port3.5
port3.7
are
not
general-purpose
I/O
ports.
They
are
dedicated
to
monitor
control
or
DAC
pins.
3.
INT1
and
T1
input
pins
are
not
provided.
4.
Port2.4
port2.7
are
shared
with
DAC
pins;
port3.0
port3.2
port3.4
are
shared
with
monitor
control
pins.
In
addition,
there
are
2
timers,
5
interrupt
sources
and
serial
interface
compatible
with
the
standard
8051.
The
Txd/Rxd
(P3./P3.1)
pins
are
shared
with
DDC
interface.
INTO/TO
pins
are
shared
with
IIC
interface.
An
extra
option
can
be
used
to
switch
the
INTO
source
from
P3.2
to
P2.0.
This
feature
maintains
an
external
interrupt
source
when
IIC
interface
Page
24