Asus PRIME Z590-P WIFI Intel 500 series Channel BIOS UM English - Page 18

DRAM RTL (CHA DIMM0 Rank0) / DRAM RTL (CHA DIMM0 Rank1) / DRAM RTL (CHA DIMM1 Rank0) / DRAM RTL (CHA DIMM1 Rank1) / DRAM RTL (CHB DIMM0 Rank0) / DRAM RTL (CHB DIMM0 Rank1) / DRAM RTL (CHB DIMM1 Rank0) / DRAM RTL (CHB DIMM1 Rank1) Configuration options: [Auto] [0] - [127] DRAM IOL (CHA DIMM0 Rank0) / DRAM IOL (CHA DIMM0 Rank1) / DRAM IOL (CHA DIMM1 Rank0) / DRAM IOL (CHA DIMM1 Rank1) / DRAM IOL (CHB DIMM0 Rank0) / DRAM IOL (CHB DIMM0 Rank1) / DRAM IOL (CHB DIMM1 Rank0) / DRAM IOL (CHB DIMM1 Rank1) Configuration options: [Auto] [0] - [15] CHA IO_Latency_offset / CHB IO_Latency_offset Configuration options: [Auto] [0] - [127] CHA RFR delay / CHB RFR delay Configuration options: [Auto] [0] - [127] Memory Training Algorithms Early Command Training Configuration options: [Auto] [Disabled] [Enabled] SenseAmp Offset Training Configuration options: [Disabled] [Enabled] Early ReadMPR Timing Centering 2D Configuration options: [Disabled] [Enabled] Read MPR Training Configuration options: [Disabled] [Enabled] Receive Enable Training Configuration options: [Disabled] [Enabled] Jedec Write Leveling Configuration options: [Disabled] [Enabled] LPDDR4 Write DQ DQS Retraining Configuration options: [Disabled] [Enabled] Early Write Time Centering 2D Configuration options: [Auto] [Disabled] [Enabled] Early Read Time Centering 2D Configuration options: [Auto] [Disabled] [Enabled] Write Timing Centering 1D Configuration options: [Disabled] [Enabled] Write Voltage Centering 1D Configuration options: [Auto] [Disabled] [Enabled] Read Timing Centering 1D Configuration options: [Auto] [Disabled] [Enabled] 18 PRIME / TUF GAMING Intel® 500 Series BIOS Manual