Asus RS100-E10-PI2 User Manual - Page 75

Q-Code table, continued on the next

Page 75 highlights

4.5.2 Q-Code table Action Normal boot PHASE Security Phase PEI(Pre-EFI initialization) phase POST CODE 1 2 3 4 5 6 10 11 15 19 0 10 1B 1C 1D 1E 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 50 TYPE Progress Progress Progress Progress Progress Progress Progress Progress Progress Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress MRC Progress DESCRIPTION First post code(POWER_ON_POST_CODE) Load BSP microcode(MICROCODE_POST_CODE) Perform early platform initialization Set cache as ram for PEI phase(CACHE_ENABLED_POST_CODE) Establish Stack CPU Early init.(CPU_EARLY_INIT_POST_CODE) PEI Core Entry PEI cache as ram CPU initial NB initialize before installed memory SB initialize before installed memory MRC_INITIALIZATION_START MRC_CMD_PLOT_2D MRC_FAST_BOOT_PERMITTED MRC_RESTORE_NON_TRAINING MRC_PRINT_INPUT_PARAMS MRC_SET_OVERRIDES_PSPD MRC_SPD_PROCESSING MRC_SET_OVERRIDES MRC_MC_CAPABILITY MRC_MC_CONFIG MRC_MC_MEMORY_MAP MRC_JEDEC_INIT_LPDDR3 MRC_RESET_SEQUENCE MRC_PRE_TRAINING MRC_EARLY_COMMAND MRC_SENSE_AMP_OFFSET MRC_READ_MPR MRC_RECEIVE_ENABLE MRC_JEDEC_WRITE_LEVELING MRC_LPDDR_LATENCY_SET_B MRC_WRITE_TIMING_1D MRC_READ_TIMING_1D MRC_DIMM_ODT MRC_EARLY_WRITE_TIMING_2D MRC_WRITE_DS MRC_WRITE_EQ MRC_EARLY_READ_TIMING_2D MRC_READ_ODT MRC_READ_EQ MRC_READ_AMP_POWER MRC_WRITE_TIMING_2D MRC_READ_TIMING_2D MRC_CMD_VREF MRC_WRITE_VREF_2D MRC_READ_VREF_2D MRC_POST_TRAINING MRC_LATE_COMMAND MRC_ROUND_TRIP_LAT MRC_TURN_AROUND MRC_CMP_OPT MRC_SAVE_MC_VALUES MRC_RESTORE_TRAINING MRC_RMT_TOOL MRC_WRITE_SR MRC_DIMM_RON MRC_RCVEN_TIMING_1D MRC_MR_FILL MRC_PWR_MTR MRC_DDR4_MAPPING MRC_WRITE_VOLTAGE_1D MRC_EARLY_RDMPR_TIMING_2D MRC_FORCE_OLTM MRC_MC_ACTIVATE (continued on the next page) ASUS RS100-E10-PI2 4-17

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ASUS RS100-E10-PI2
4-17
4.5.2
Q-Code table
Action
PHASE
POST CODE
TYPE
DESCRIPTION
Normal boot
Security Phase
1
Progress
First post code(POWER_ON_POST_CODE)
2
Progress
Load BSP microcode(MICROCODE_POST_CODE)
3
Progress
Perform early platform initialization
4
Progress
Set cache as ram for PEI phase(CACHE_ENABLED_POST_CODE)
5
Progress
Establish Stack
6
Progress
CPU Early init.(CPU_EARLY_INIT_POST_CODE)
PEI(Pre-EFI
initialization) phase
10
Progress
PEI Core Entry
11
Progress
PEI cache as ram CPU initial
15
Progress
NB initialize before installed memory
19
Progress
SB initialize before installed memory
0
MRC Progress
MRC_INITIALIZATION_START
10
MRC Progress
MRC_CMD_PLOT_2D
1B
MRC Progress
MRC_FAST_BOOT_PERMITTED
1C
MRC Progress
MRC_RESTORE_NON_TRAINING
1D
MRC Progress
MRC_PRINT_INPUT_PARAMS
1E
MRC Progress
MRC_SET_OVERRIDES_PSPD
20
MRC Progress
MRC_SPD_PROCESSING
21
MRC Progress
MRC_SET_OVERRIDES
22
MRC Progress
MRC_MC_CAPABILITY
23
MRC Progress
MRC_MC_CONFIG
24
MRC Progress
MRC_MC_MEMORY_MAP
25
MRC Progress
MRC_JEDEC_INIT_LPDDR3
26
MRC Progress
MRC_RESET_SEQUENCE
27
MRC Progress
MRC_PRE_TRAINING
28
MRC Progress
MRC_EARLY_COMMAND
29
MRC Progress
MRC_SENSE_AMP_OFFSET
2A
MRC Progress
MRC_READ_MPR
2B
MRC Progress
MRC_RECEIVE_ENABLE
2C
MRC Progress
MRC_JEDEC_WRITE_LEVELING
2D
MRC Progress
MRC_LPDDR_LATENCY_SET_B
2E
MRC Progress
MRC_WRITE_TIMING_1D
2F
MRC Progress
MRC_READ_TIMING_1D
30
MRC Progress
MRC_DIMM_ODT
31
MRC Progress
MRC_EARLY_WRITE_TIMING_2D
32
MRC Progress
MRC_WRITE_DS
33
MRC Progress
MRC_WRITE_EQ
34
MRC Progress
MRC_EARLY_READ_TIMING_2D
35
MRC Progress
MRC_READ_ODT
36
MRC Progress
MRC_READ_EQ
37
MRC Progress
MRC_READ_AMP_POWER
38
MRC Progress
MRC_WRITE_TIMING_2D
39
MRC Progress
MRC_READ_TIMING_2D
3A
MRC Progress
MRC_CMD_VREF
3B
MRC Progress
MRC_WRITE_VREF_2D
3C
MRC Progress
MRC_READ_VREF_2D
3D
MRC Progress
MRC_POST_TRAINING
3E
MRC Progress
MRC_LATE_COMMAND
3F
MRC Progress
MRC_ROUND_TRIP_LAT
40
MRC Progress
MRC_TURN_AROUND
41
MRC Progress
MRC_CMP_OPT
42
MRC Progress
MRC_SAVE_MC_VALUES
43
MRC Progress
MRC_RESTORE_TRAINING
44
MRC Progress
MRC_RMT_TOOL
45
MRC Progress
MRC_WRITE_SR
46
MRC Progress
MRC_DIMM_RON
47
MRC Progress
MRC_RCVEN_TIMING_1D
48
MRC Progress
MRC_MR_FILL
49
MRC Progress
MRC_PWR_MTR
4A
MRC Progress
MRC_DDR4_MAPPING
4B
MRC Progress
MRC_WRITE_VOLTAGE_1D
4C
MRC Progress
MRC_EARLY_RDMPR_TIMING_2D
4D
MRC Progress
MRC_FORCE_OLTM
50
MRC Progress
MRC_MC_ACTIVATE
(continued on the next page)