Epson 2080 Service Manual - Page 25
System Reset Circuit
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LQ-2080 2.3.1 System Reset Circuit Control circuits IC3 and IC4 are initialized when a /RESET signal (LOW level) is output from port 1 (VOUT) of IC2. IC2 monitors the +5 V line on port 3, and resets under the following conditions: 1. When the power supply is turned on, a /RESET signal is output. /RESET is canceled when the +5 V line goes up to 4.2 V, and then 100 ms passes. 2. When the +5 V line goes below +4.2 V, a /RESET signal is output. /RESET is canceled when the +5 V line goes back up to 4.2 V and then 100 ms passes. Revision A Figure 2-3. Reset Circuit Operating Principles Figure 2-4. Reset Signal Output Timing Control Circuit 25
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LQ-2080
Revision A
Operating Principles
Control Circuit
25
2.3.1
System Reset Circuit
Control circuits IC3 and IC4 are initialized when a /RESET signal (LOW
level) is output from port 1 (VOUT) of IC2. IC2 monitors the +5 V line on
port 3, and resets under the following conditions:
1.
When the power supply is turned on, a /RESET signal is output.
/RESET is canceled when the +5 V line goes up to 4.2 V, and then
100 ms passes.
2.
When the +5 V line goes below +4.2 V, a /RESET signal is output.
/RESET is canceled when the +5 V line goes back up to 4.2 V and
then 100 ms passes.
Figure 2-3.
Reset Circuit
Figure 2-4.
Reset Signal Output Timing
V
O
U
T
M
R
E
S
V
C
C
G
N
D
+5V
+5V
R
63
1K
IC
2
P
S
T5920
C
36
0 .1 U
IC
4
IC
3
E
05B
24Y
A
TP
M
96C
041A
F
2 3
R
E
S
E
T
74
R
E
S
E
T
1
2
3
4
1
2
3
4
5
V
C
C
(+5V
lin e )
V
O
U
T (R
E
S
E
T)
R
E
S
E
T
R
E
S
E
T
P
ow
e r O
n
(v)
100m
s
100m
s