Epson 2080 Service Manual - Page 29

PF Motor Driver Circuit, EEPROM Control Circuit - lq printer driver

Page 29 highlights

LQ-2080 2.3.4 PF Motor Driver Circuit The figure below shows the PF motor driver circuit. Revision A 2.3.5 EEPROM Control Circuit The EEPROM is nonvolatile memory that stores information even if the printer power is off. The figure below shows the EEPROM control circuit. Figure 2-7. PF Motor Driver Circuit The PF driver current is controlled on the Gate Array and the signals are output via port 123 (PFI0A), port 121 (PFI1A), port 120 (PFI0B), and port 118 (PFI1B). Figure 2-8. EEPROM Control Circuit The EEPROM is controlled by CPU ports 9 (P70), 10 (P71), 11 (P72), and 12 (P73). Port 11 is the data output line used to save the information to the EEPROM, and port 12 is the data input line used to read the saved data from the EEPROM. Port 70 is the chip select line, and port 71 is the clock timing line. When the PWDN signal (power down) is detected on port 20 (INTO), the CPU writes the necessary data to the EEPROM before the +5 V line drops to 4.75 V. Operating Principles Control Circuit 29

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LQ-2080
Revision A
Operating Principles
Control Circuit
29
2.3.4
PF Motor Driver Circuit
The figure below shows the PF motor driver circuit.
Figure 2-7.
PF Motor Driver Circuit
The PF driver current is controlled on the Gate Array and the signals are
output via port 123 (PFI0A), port 121 (PFI1A), port 120 (PFI0B), and
port 118 (PFI1B).
2.3.5
EEPROM Control Circuit
The EEPROM is nonvolatile memory that stores information even if the
printer power is off. The figure below shows the EEPROM control
circuit.
Figure 2-8.
EEPROM Control Circuit
The EEPROM is controlled by CPU ports 9 (P70), 10 (P71), 11 (P72),
and 12 (P73). Port 11 is the data output line used to save the
information to the EEPROM, and port 12 is the data input line used to
read the saved data from the EEPROM. Port 70 is the chip select line,
and port 71 is the clock timing line. When the PWDN signal (power
down) is detected on port 20 (INTO), the CPU writes the necessary data
to the EEPROM before the +5 V line drops to 4.75 V.
E
05B
4 2 ( IC
3)
P
F I0 A
P
F I1 A
P
F I0 B
P
F I1 B
123
121
120
118
C
N
11
C
R
A
C
R
-A
C
R
B
C
R
-B
P
H
A
S
E
A
P
H
A
S
E
B
122
119
2
1
23
24
IN
A
IN
-A
IN
B
IN
-B
A
-A
B
-B
A
2 9 1 7 ( IC
12)
43
26
6
3
18
21
P
H
1
P
H
2
/P
FH
O
LD
124
44
25
V
R
E
F1
V
R
E
F2
1
3
2
4
C
P
U
P
70
P
71
P
72
P
73
C
S
C
K
D
I
D
O
E
E
P
R
O
M
9
10
11
12
1
2
3
4
IC
5