HP ProLiant DL380p DDR3 memory technology - Page 2

Abstract DDR3 uses a variety of technologies that improve performance and capacities over DDR2 memory. This technology brief provides a detailed look at the core technologies used in DDR3 memory and its integration with the newer server architectures using distributed memory and on-processor memory controllers. It is intended for technical professionals who need to understand DDR3 memory technology. DDR3 architecture DDR3 uses the same basic DRAM configuration and architecture as previous DDR implementations. The basic DIMM consists of ranks of 9 or 18 DRAMs that deliver 72 bits (64 data and 8 ECC) in parallel to the memory bus to the CPU. DDR3 supports addressing up to eight total banks, or ranks, of memory on a given memory channel. An individual DIMM module can be designed to support one, two, or four banks of these DRAMs, creating what are commonly referred to as single-, dual-, or quadranked DIMM modules. Overall capacity of a DIMM is determined by the capacity of the DRAMs used and the number of ranks it contains. DDR3 defines up to an 8 Gigabit DRAM, which will eventually lead to individual DDR3 quad rank DIMMs with capacities as large as 64 GB. Types of DDR3 DIMMs DDR3 supports both Unbuffered and Registered DIMMs. With Unbuffered DIMMs (UDIMMs), all address and control signals, as well as the data lines, are connected directly to the memory controller across the DIMM connector. Each additional UDIMM installed on a memory channel increases the electrical load. The result is that DDR3-based memory controllers can support a maximum of two dualrank UDIMMs per memory channel. Registered DIMMs (RDIMMs) lessen the direct electrical loading by adding a register on the DIMM to buffer the Address and Command signals between the DRAMs and the memory controller. The register on each DIMM bears the electrical load for the address bus to the DRAMs, reducing the overall load on the address portion of the memory channel. The data from RDIMMs is still delivered in parallel as 72 bits (64 data + 8 ECC) across the data portion of the memory bus. With RDIMMs, each memory channel can support up to 3 dual-rank DDR3 RDIMMs or 2 quad-rank RDIMMs. Fully Buffered DIMMs (FBDIMMs), which buffer all memory signals (address, control, and data) through an Advanced Memory Buffer (AMB) chip installed on each DIMM, have not been implemented for DDR3. The FBDIMM architecture was primarily designed to increase the maximum memory for servers by allowing more DIMMs to be installed on each memory channel. However, FBDIMMs were more expensive, used more power, and had increased latency compared to other DIMMs. The new Non-uniform Memory Access (NUMA) architectures support large memory sizes by having separate memory controllers and multiple memory channels located on each processor. This has eliminated the need to support large numbers of DIMMs on a single channel and made FBDIMMs unnecessary. DDR3 memory speeds DDR3 memory features significantly faster clocking and data rate than DDR2 memory. The DDR3 specification defines data rates of up to 1600 Megatransfers per second (MT/s), which is twice the rate of the fastest DDR2 memory speed (Table 1). 2