HP ProLiant DL380p DDR3 memory technology - Page 9

Figure 5. Intel Xeon 5500 series memory architecture NUMA architecture is designed to address two related problems that have emerged as system complexity has grown:  Eliminating bottlenecks in the memory subsystem that constrain system memory throughput  Supporting larger memory footprints without significantly lowering memory performance DDR3 integrates with this architecture to help deliver significantly improved memory throughput. With the current maximum transfer rate of 1333 Megatransfers per second (MT/s), DDR3 memory can potentially deliver 10.6 GB/s of bandwidth per channel. The new architecture also supports more memory controllers and channels. For example, using DDR3 memory with six channels, the architecture for the Intel-based 2P ProLiant G6 servers has a maximum theoretical memory bandwidth of 64 GB/s, 65% greater than that of the older architecture using DDR2 memory. DDR3 and Intel 4P architecture Figure 6 shows the processor/memory architecture for the 4P HP ProLiant G7 servers that use Intel Xeon 5600 series processors. While the basic NUMA architecture is apparent, there are distinct differences between this and the design of Intel 2P systems. The most significant difference is the existence of separate memory buffers between the CPU and the memory channels. The buffers use a proprietary high speed serial link to transport memory data between themselves and the CPU while providing a standard memory bus interface to the DDR3 DIMMs. This arrangement allows each memory controller to support two memory channels of two DIMMs each. Unlike the 2P architecture this design also supports four memory controllers per CPU. Taken together, these allow the new Intelbased 4P systems to support up to sixty-four DIMMs, or 1 Terabyte of memory using 16 GB DIMMs. 9