HP ProLiant DL380p DDR3 memory technology - Page 8

Figure 4. Intel 2P Architecture with front side bus Intel 2P Memory Architecture with Front Side Bus CPU Front Side Bus CPU Front Side Bus Memory Channels (4) System Chipset Under this architecture, each memory channel has a maximum total raw bandwidth of 9.6 GB/s for systems supporting PC2-6400 fully buffered DIMMs. The memory channels of systems that use registered DIMMs can support a maximum bandwidth of 6.4 GB/s. With four memory channels per system, the theoretical maximum memory bandwidth for these systems is 38.4 GB/s and 25.6 GB/s, respectively. There are, however, factors that limit the achievable throughput:  The maximum bandwidth of the front side bus becomes a choke point.  Larger memory footprints require fully buffered DIMMS, which increase memory latency and decrease memory throughput and performance. DDR3 and the new systems architecture Although they vary slightly in their implementation details, NUMA architectures share a common design concept. With NUMA, each processor in the system has its own separate memory controllers and memory channels. In addition to increasing the total number of memory controllers and memory channels in the system, each processor can access its attached memory directly. This eliminates the bottleneck of the front side bus and also reduces latency. A given processor accesses the system memory attached to a different processor through high-speed serial links that connect the primary system components. In Intel-based systems, this is the QuickPath Interconnect (QPI). For AMD-based systems, it is the HyperTransport technology. All of the new systems use DDR3 memory to help increase memory throughput. 8