HP ProLiant DL380p DDR3 memory technology - Page 7

DDR3 memory and NUMA systems architectures

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Figure 3. DDR3 DIMM with temperature sensor HP engineers have performed extensive modeling and testing to determine the operating temperature for each of the DRAMs on the DIMM. These temperature values are derived by evaluating three factors:  the measured temperature from the DIMM sensor  the relative location of each DRAM on the DIMM  the direction of the airflow across the DIMM in a given server system All of this information is integrated into the "Sea of Sensors" fan control technology that is part of all HP ProLiant G6 and G7 servers. This technology ensures optimal cooling which helps prevent possible system failure and reduces power consumption by eliminating overcooling. DDR3 memory and NUMA systems architectures DDR3 is a standalone memory specification; however, its use in servers is in many ways associated with the evolution of new server architectures, which feature Non-Uniform Memory Access (NUMA). AMD-based servers have used NUMA architecture since their inception, using DDR1and later DDR2 memory. The new AMD-based ProLiant G7 servers continue to use a NUMA architecture that has been updated to support DDR3 memory. Intel-based HP ProLiant G6 and G7 servers now incorporate NUMA architecture along with other new features. The new server architectures and DDR3 are designed to address memory throughput and latency issues that were limiting system performance under older architectures as system memory footprints continued to increase. Older server architectures Figure 4 outlines a view of the previous architecture for two-processor (2P) Intel-based systems. With the traditional 2P architecture, memory controllers and memory channels are located on a centralized system chipset. This architecture used uniform memory access in which each processor used the same pathway to access all of the system memory. Processors communicate with the memory controllers across the front side bus. The memory controllers then access the DIMMs on the memory channels, returning the requested data to the processors. The architecture supports two memory controller functions, each of which manage two memory channels, giving a total of four memory channels per system. Large memory footprints may be achieved by using up to four DDR2 FBDIMMs per channel. 7

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Figure 3.
DDR3 DIMM with temperature sensor
HP engineers have performed extensive modeling and testing to determine the operating temperature
for each of the DRAMs on the DIMM. These temperature values are derived by evaluating three
factors:
the measured temperature from the DIMM sensor
the relative location of each DRAM on the DIMM
the direction of the airflow across the DIMM in a given server system
All of this information is integrated into the “Sea of Sensors” fan control technology that is part of all
HP ProLiant G6 and G7 servers. This technology ensures optimal cooling which helps prevent possible
system failure and reduces power consumption by eliminating overcooling.
DDR3 memory and NUMA systems architectures
DDR3 is a standalone memory specification; however, its use in servers is in many ways associated
with the evolution of new server architectures, which feature Non-Uniform Memory Access (NUMA).
AMD-based servers have used NUMA architecture since their inception, using DDR1and later DDR2
memory. The new AMD-based ProLiant G7 servers continue to use a NUMA architecture that has
been updated to support DDR3 memory. Intel-based HP ProLiant G6 and G7 servers now incorporate
NUMA architecture along with other new features. The new server architectures and DDR3 are
designed to address memory throughput and latency issues that were limiting system performance
under older architectures as system memory footprints continued to increase.
Older server architectures
Figure 4 outlines a view of the previous architecture for two-processor (2P) Intel-based systems. With
the traditional 2P architecture, memory controllers and memory channels are located on a centralized
system chipset. This architecture used uniform memory access in which each processor used the same
pathway to access all of the system memory. Processors communicate with the memory controllers
across the front side bus. The memory controllers then access the DIMMs on the memory channels,
returning the requested data to the processors. The architecture supports two memory controller
functions, each of which manage two memory channels, giving a total of four memory channels per
system. Large memory footprints may be achieved by using up to four DDR2 FBDIMMs per channel.