HP Vectra XA 5/xxx HP Vectra xA 5/XXX Series 5 /vl 5/xxx series 5 pc Technical - Page 22

Chip-Set

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2 System Board Chip-Set PL Bus Interface Chip-Set The chip-set comprises three chips. These interface between the three main buses (the Processor-Local bus, the PCI bus and the ISA bus). • The TXC chip (82439HX) is a combined PL/PCI bridge and cache controller and main memory controller and PCI-to-PL bus data path. • The PIIX3 chip (82371SB) is a combined PCI/ISA bridge and IDE controller and USB controller. • The Super I/O chip (37C932) is a combined serial interface and parallel interface and keyboard controller and mouse controller and flexible disk drive controller. The TXC and PIIX3 chips are PCI 2.1 compliant, and provide for PCI Concurrency. Concurrent data transfers that do not contest for the same resources (such as processor to memory concurrent with PCI peer to peer, or processor to ISA device concurrent with PCI device to memory) are allowed to interleave their transfers more finely than with previous chip sets. This has little effect on the throughput of the system, but results in a greatly reduced worst-case latency. This leads to a much smoother operation of video capture, MPEG clips and audio clips. To find out more about how this is achieved, the reader is referred to the Intel documentation on the 82430HX chip set. Relevant key words include: the multi-transaction timer (MTT), the passive release mechanism, and the PCI delayed transaction mechanism. PL/PCI Bridge Chip (82439HX) The bridge between the Processor Local Bus (PL Bus) and the PCI Bus is encapsulated in a 324 pin ball grid array (BGA) package. The TXC chip monitors each cycle that is initiated by the processor, and forwards those to the PCI bus that are not targeted at the local memory. It translates PL bus cycles into PCI bus cycles. The chip supports the SMM mode of the Pentium processor, the CPU stop clock hardware function, and the keyboard lock function. These are used by the LittleBen chip, as described on page 73. 22

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22
2
System Board
Chip-Set
Chip-Set
The chip-set comprises three chips. These interface between the three main
buses (the Processor-Local bus, the PCI bus and the ISA bus).
•
The TXC chip (82439HX) is a combined
PL/PCI bridge
and
cache
controller
and
main memory controller
and
PCI-to-PL bus data path
.
•
The PIIX3 chip (82371SB) is a combined
PCI/ISA bridge
and
IDE
controller
and
USB controller
.
•
The Super I/O chip (37C932) is a combined
serial interface
and
parallel
interface
and
keyboard controller
and
mouse controller
and
flexible
disk drive controller
.
The TXC and PIIX3 chips are PCI 2.1 compliant, and provide for
PCI
Concurrency
. Concurrent data transfers that do not contest for the same
resources (such as processor to memory concurrent with PCI peer to peer,
or processor to ISA device concurrent with PCI device to memory) are
allowed to interleave their transfers more finely than with previous chip
sets. This has little effect on the throughput of the system, but results in a
greatly reduced worst-case latency. This leads to a much smoother
operation of video capture, MPEG clips and audio clips.
To find out more about how this is achieved, the reader is referred to the
Intel documentation on the 82430HX chip set. Relevant key words include:
the
multi-transaction timer
(MTT), the
passive release
mechanism, and
the
PCI delayed transaction
mechanism.
PL/PCI Bridge Chip (
82439HX
)
The bridge between the Processor Local Bus (PL Bus) and the PCI Bus is
encapsulated in a 324 pin ball grid array (BGA) package.
PL Bus Interface
The TXC chip monitors each cycle that is initiated by the processor, and
forwards those to the PCI bus that are not targeted at the local memory. It
translates PL bus cycles into PCI bus cycles.
The chip supports the SMM mode of the Pentium processor, the CPU stop
clock hardware function, and the keyboard lock function. These are used by
the LittleBen chip, as described on page 73.