HP Vectra XA 5/xxx HP Vectra xA 5/XXX Series 5 /vl 5/xxx series 5 pc Technical - Page 33

2 System Board Devices on the Processor-Local Bus Each bank that is used must contain a pair of identical modules: the same speed (60 or 70 ns), the same width (32-bit or 36-bit), and the same technology (extended data out, EDO, or fast page mode, FPM). Different banks can contain different speed modules (but the computer will work at the speed of the slowest bank). Different banks can contain different width modules (but parity and error correcting codes, ECC, are not enabled if any 32-bit width pairs of modules are used). Different banks can contain different technology modules. The following table indicates the recommended capacities of main memory. Operating System Windows 3.11 Windows 95 Windows NT OS/2 Minimum Memory Capacity 4 to 8 MB 8 MB 12 MB 4 to 8 MB Recommended Memory Capacity 12 to 16 MB 16 to 24 MB 24 to 32 MB 16 MB The Setup program automatically detects which memory module capacity, speed, and type is installed in each bank. Individual pages of memory can be configured as cacheable or non-cacheable by software or hardware. They can also be enabled and disabled by hardware or software. Error Correcting Code Operation Error correcting code (ECC) is available when using 36-bit memory modules. The original 32-bit modules must be removed so that the memory is populated exclusively by 36-bit modules. The appropriate field must be set in the Memory sub-menu of the Configuration menu of the Setup program. Using ECC, a single bit error in any 72-bit line of memory (64 data bits plus 8 parity bits) is corrected automatically and transparently. A double bit error causes an NMI to be generated, and the computer to be halted. If more than two bits are faulty within any given 72-bit line, the effect is the same as it would have been without error correction. The effect of executing a faulty instruction is always unpredictable, and might cause the program to 'hang'. The effect of reading a faulty data word is often similarly unpredictable, but can sometimes be tolerated (for instance, it might merely appear as a corrupted pixel on a video display). An extra delay is introduced in the chip set while it is performing the ECC conversions, so causing ECC memory to have a slower access than non-ECC memory. Moreover, ECC memory modules are available only in 70 ns FPM technology. 33