Hitachi DK23DA-30F Owners Manual - Page 105
Sustained Ultra DMA Write Data
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HSTROBE at host DD(15:0) at host Figure 6-14 Sustained Ultra DMA Write Data tCYC t2CYC tCYC t2CYC tDVH tDVHIC tDVS tDVSIC tDVH tDVHIC tDVS tDVSIC tDVH tDVHIC HSTROBE at device DD(15:0) at device tDH tDHIC tDS tDSIC tDH tDHIC tDS tDSIC tDH tDHIC Note: DD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host. Mode 0(ns) Mode 1(ns) Mode 2(ns) Mode 3(ns) Mode 4(ns) Mode5(ns) Description SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tCYC 112 73 54 39 25 16.8 Cycle time allowing for asymmetry and clock variation t2CYC 230 153 115 86 57 38 Two cycle time allowing for clock variation tDS 15 10 7 7 5 4 Data setup time at recipient tDH 5 5 5 5 5 4.6 Data hold time at recipient tDVS 70 48 31 20 6.7 4.8 Data valid setup time at sender tDVH 6.2 6.2 6.2 6.2 6.2 4.8 Data valid hold time at sender tDSIC 14.7 9.7 6.8 6.8 4.8 tDHIC 4.8 4.8 4.8 4.8 4.8 tDVSIC 72.9 50.9 33.9 22.6 9.5 2.3 Recipient IC data setup time 2.8 Recipient IC data hold time 6.0 Sender IC data valid setup time tDVHIC 9 9 9 9 9 6 Sender IC data valid hold time K6602705 Rev.3 08.20.01 - 105 -