LG KE600 Service Manual - Page 63

Receiver part, 21. Transmitter part

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3. TECHNICAL BRIEF 3.20. Receiver part Figure 37 Receiver part block diagram The constant gain direct conversion receiver contains all active circuits for a complete receiver chain for GSM/GPRS/EDGE (see Figure 37). The GSM850/900/DCS1800/ PCS1900 LNAs with balanced inputs are fully integrated. No inter-stage filtering is needed. The orthogonal LO signals are generated by a divider-by-four for GSM850/900 band and a divider-by-two for the DCS1800/PCS1900 band. Down conversion to baseband domain is performed by low/high band quadrature direct down conversion mixers. The baseband chain contains a LNB (low noise buffer), channel filter, output buffer and DC-offset compensation. The 3rd order low pass filter is fully integrated and provides sufficient suppression of blocking signals as well as adjacent channel interferers and avoids anti-aliasing through the baseband ADC. The receive path is fully differential to suppress on-chip interferences. Several gain steps are implemented to cope with the dynamic range of the input signals. Depending on the baseband ADC dynamic range, single- or multiple gain step switching schemes are applicable. Furthermore an automatic DC-offset compensation can be used (depending on the gain setting) to reduce the DC-offset at baseband-output. A programmable gain correction can be applied to correct for front end- and receiver gain tolerances. 3.21. Transmitter part The GMSK transmitter supports power class 4 for GSM850 and GSM900 as well as power class 1 for DCS1800 and PCS1900. The digital transmitter architecture is based on a very low power fractional-N Sigma-Delta synthesizer without any external components (see Figure39). The analog I/Q modulation data from the baseband is converted to digital, filtered and transformed to polar coordinates. The phase/frequency signal is further on processed by the Sigma-Delta modulation loop. The output of its associated VCO is divided by four or two, respectively, and connected via an output buffer to the appropriate single ended output pin. This configuration ensures minimum noise level. The 8PSK transmitter supports power class E2 for GSM850 and GSM900 as well as for DCS1800 and PCS1900. - 64 -

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3. TECHNICAL BRIEF
- 64 -
3.20. Receiver part
The constant gain direct conversion receiver contains all active circuits for a complete receiver chain
for GSM/GPRS/EDGE (see Figure 37). The GSM850/900/DCS1800/ PCS1900 LNAs with balanced
inputs are fully integrated. No inter-stage filtering is needed. The orthogonal LO signals are generated
by a divider-by-four for GSM850/900 band and a divider-by-two for the DCS1800/PCS1900 band.
Down conversion to baseband domain is performed by low/high band quadrature direct down
conversion mixers. The baseband chain contains a LNB (low noise buffer), channel filter, output buffer
and DC-offset compensation. The 3rd order low pass filter is fully integrated and provides sufficient
suppression of blocking signals as well as adjacent channel interferers and avoids anti-aliasing
through the baseband ADC. The receive path is fully differential to suppress on-chip interferences.
Several gain steps are implemented to cope with the dynamic range of the input signals. Depending
on the baseband ADC dynamic range, single- or multiple gain step switching schemes are applicable.
Furthermore an automatic DC-offset compensation can be used (depending on the gain setting) to
reduce the DC-offset at baseband-output. A programmable gain correction can be applied to correct
for front end- and receiver gain tolerances.
3.21. Transmitter part
The GMSK transmitter supports power class 4 for GSM850 and GSM900 as well as power class 1 for
DCS1800 and PCS1900. The digital transmitter architecture is based on a very low power fractional-N
Sigma-Delta synthesizer without any external components (see Figure39). The analog I/Q modulation
data from the baseband is converted to digital, filtered and transformed to polar coordinates. The
phase/frequency signal is further on processed by the Sigma-Delta modulation loop. The output of its
associated VCO is divided by four or two, respectively, and connected via an output buffer to the
appropriate single ended output pin. This configuration ensures minimum noise level. The 8PSK
transmitter supports power class E2 for GSM850 and GSM900 as well as for DCS1800 and PCS1900.
Figure 37 Receiver part block diagram