MSI K9N SLI-F User Guide - Page 66
Row to Row delay TRRD
UPC - 816909043235
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MS-7250 Mainboard MCT Timing Mode This field has the capacity to automatically detect all of the DRAM timing. If you set this field to [Manual], the following fields will be selectable. CAS Latency (TCL) W hen the MCT Timing M ode is set to [Manual], the field is adjustable.This controls the CAS latency, which determines the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. Min RAS# Active Time (TRAS) W hen the MCT Timing Mode is set to [Manual], the field is adjustable. This setting determines the time RAS takes to read from and write to a memory cell. Row Precharge Time (TRP) W hen the MCT Timing Mode is set to [Manual], the field is adjustable. This item controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refreshing may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. RAS# to CAS# delay (TRCD) W hen the MCT Timing Mode is set to [Manual], the field is adjustable. W hen DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. Row to Row delay (TRRD) W hen the MCT Timing Mode is set to [Manual], the field is adjustable. Specifies the active-to-active delay of different banks. Row cycle time (TRC) W hen the MCT Timing Mode is set to [Manual], the field is adjustable. The row cycle time determines the minimum number of clock cycles a memory row takes to complete a full cycle, from row activation up to the precharging of the active row. Row refresh Cycle time (TRFC) W hen the MCT Timing Mode is set to [Manual], the field is adjustable. Autorefresh -active to RAS#-active or RAS# auto-refresh. Read to Write delay (TRWT) W hen the MCT Timing Mode is set to [Manual], the field is adjustable. This is not a DRAM-specified timing parameter, but must be considered due to routing latencies on the clock forwarded bus. It is counted from the first address bus slot that was not associated with part of the read burst. 3-24