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Power Management, AMD Athlon™ XP Processor Model 10 Data Sheet

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26237C-May 2003 Chapter 4 Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet must first connect the system bus. Connecting the system bus places the processor into the higher power probe state. After the Northbridge has completed all probes of the processor, the Northbridge must disconnect the AMD Athlon system bus again so that the processor can return to the low-power state. During the Stop Grant states, the processor latches INIT#, INTR, NMI, SMI#, or a local APIC interrupt message, if they are asserted. The Stop Grant state is exited upon the deassertion of STPCLK# or the assertion of RESET#. When STPCLK# is deasserted, the processor initiates a connect of the AMD Athlon system bus if it is disconnected. After the processor enters the Working state, any pending interrupts are recognized and serviced and the processor resumes execution at the instruction boundary where STPCLK# was initially recognized. If RESET# is sampled asserted during the Stop Grant state, the processor exits the Stop Grant state and the reset process begins. There are two mechanisms for asserting STPCLK#-hardware and software. The Southbridge can force STPCLK# assertion for throttling to protect the processor from exceeding its maximum case temperature. This is accomplished by asserting the THERM# input to the Southbridge. Throttling asserts STPCLK# for a percentage of a predefined throttling period: STPCLK# is repetitively asserted and deasserted until THERM# is deasserted. Software can force the processor into the Stop Grant state by accessing ACPI-defined registers typically located in the Southbridge. The operating system places the processor into the C2 Stop Grant state by reading the P_LVL2 register in the Southbridge. If an ACPI Thermal Zone is defined for the processor, the operating system can initiate throttling with STPCLK# using the ACPI defined P_CNT register in the Southbridge. The Northbridge connects the AMD Athlon system bus, and the processor enters the Probe state to service cache snoops during Stop Grant for C2 or throttling. Power Management 11

Section	Page
Table of Contents	3
List of Figures	7
List of Tables	9
Revision History	11
1 Overview	13
1.1 QuantiSpeed™ Architecture Summary	14
2 Interface Signals	17
2.1 Overview	17
2.2 Signaling Technology	17
2.3 Push-Pull (PP) Drivers	18
2.4 AMDAthlon™ System Bus Signals	18
3 Logic Symbol Diagram	19
4 Power Management	21
4.1 Power Management States	21
Working State	22
Halt State	22
Stop Grant States	22
Probe State	24
4.2 Connect and Disconnect Protocol	24
Connect Protocol	24
Connect State Diagram	28
4.3 Clock Control	30
5 CPUID Support	31
6 Advanced 333 Front-Side Bus AMDAthlon™ XP Processor Model 10 Specifications	33
6.1 Electrical and Thermal Specifications for the Advanced 333 FSB AMDAthlon™ XP Processor Model 10	33
6.2 Advanced 333 FSB AMDAthlon™ XP Processor Model 10 SYSCLK and SYSCLK# AC Characteristics	34
6.3 Advanced 333 FSB AMDAthlon™ System Bus AC Characteristics	35
6.4 Advanced 333 FSB AMDAthlon™ System Bus DC Characteristics	36
7 Advanced 400 Front-Side Bus AMDAthlon™ XP Processor Model 10 Specifications	37
7.1 Electrical and Thermal Specifications for the Advanced 400 FSB AMDAthlon™ XP Processor Model 10	37
7.2 Advanced 400 FSB AMDAthlon™ XP Processor Model 10 SYSCLK and SYSCLK# AC Characteristics	38
7.3 Advanced 400 FSB AMDAthlon™ System Bus AC Characteristics	39
7.4 Advanced 400 FSB AMDAthlon™ System Bus DC Characteristics	40
8 Electrical Data	41
8.1 Conventions	41
8.2 Interface Signal Groupings	41
8.3 Voltage Identification (VID[4:0])	42
8.4 Frequency Identification (FID[3:0])	43
8.5 VCCA AC and DC Characteristics	43
8.6 Decoupling	43
8.7 VCC_CORE Characteristics	44
8.8 Absolute Ratings	46
8.9 SYSCLK and SYSCLK# DC Characteristics	47
8.10 General AC and DC Characteristics	48
8.11 Open Drain Test Circuit	50
8.12 Thermal Diode Characteristics	51
Thermal Diode Electrical Characteristics	51
Thermal Protection Characterization	51
8.13 APIC Pins AC and DC Characteristics	53
9 Signal and PowerUp Requirements	55
9.1 PowerUp Requirements	55
Signal Sequence and Timing Description	55
Clock Multiplier Selection (FID[3:0])	58
9.2 Processor Warm Reset Requirements	58
Northbridge Reset Pins	58
10 Mechanical Data	59
10.1 Die Loading	59
10.2 AMDAthlon™ XP Processor Model 10 Part Number 27488 OPGA Package Dimensions	60
10.3 AMDAthlon™ XP Processor Model 10 Part Number 27493 OPGA Package Dimensions	62
11 Pin Descriptions	65
11.1 Pin Diagram and Pin Name Abbreviations	65
11.2 Pin List	75
11.3 Detailed Pin Descriptions	84
A20M# Pin	84
AMD Pin	84
AMDAthlon™ System Bus Pins	84
Analog Pin	84
APIC Pins, PICCLK, PICD[1:0]#	84
CLKFWDRST Pin	84
CLKIN, RSTCLK (SYSCLK) Pins	85
CONNECT Pin	85
COREFB and COREFB# Pins	85
CPU_PRESENCE# Pin	85
DBRDY and DBREQ# Pins	85
FERR Pin	85
FID[3:0] Pins	86
FSB_Sense[1:0] Pins	87
FLUSH# Pin	87
IGNNE# Pin	87
INIT# Pin	87
INTR Pin	88
JTAG Pins	88
K7CLKOUT and K7CLKOUT# Pins	88
Key Pins	88
NC Pins	88
NMI Pin	88
PGA Orientation Pins	88
PLL Bypass and Test Pins	88
PWROK Pin	88
SADDIN[1:0]# and SADDOUT[1:0]# Pins	89
Scan Pins	89
SMI# Pin	89
STPCLK# Pin	89
SYSCLK and SYSCLK#	89
THERMDA and THERMDC Pins	89
VCCA Pin	89
VID[4:0] Pins	89
VREFSYS Pin	90
ZN and ZP Pins	90
12 Ordering Information	91
Standard AMDAthlon™ XP Processor Model 10 Products	91
Thermal Diode Calculations	93
Ideal Diode Equation	93
Temperature Offset Correction	94
Conventions and Abbreviations	97
Signals and Bits	97
Data Terminology	98
Abbreviations and Acronyms	99

Match case Limit results 1 per page

Chapter 4

Power Management

26237C—May 2003

AMD Athlon™ XP Processor Model 10 Data Sheet

Preliminary Information

must first connect the system bus.

Connecting the system bus

places the processor into the higher power probe state. After

the Northbridge has completed all probes of the processor, the

Northbridge must disconnect the AMD Athlon system bus

again so that the processor can return to the low-power state.

During the Stop Grant states, the processor latches INIT#,

INTR, NMI, SMI#, or a local APIC interrupt message, if they are

asserted.

The Stop Grant state is exited upon the deassertion of

STPCLK# or the assertion of RESET#. When STPCLK# is

deasserted, the processor initiates a connect of the

AMD Athlon system bus if it is disconnected. After the

processor enters the Working state, any pending interrupts are

recognized and serviced and the processor resumes execution

at the instruction boundary where STPCLK# was initially

recognized. If RESET# is sampled asserted during the Stop

Grant state, the processor exits the Stop Grant state and the

reset process begins.

There are two mechanisms for asserting STPCLK#—hardware

and software.

The Southbridge can force STPCLK# assertion for throttling to

protect the processor from exceeding its maximum case

temperature. This is accomplished by asserting the THERM#

input to the Southbridge. Throttling asserts STPCLK# for a

percentage of a predefined throttling period: STPCLK# is

repetitively asserted and deasserted until THERM# is

deasserted.

Software can force the processor into the Stop Grant state by

accessing ACPI-defined registers typically located in the

Southbridge.

The operating system places the processor into the C2 Stop

Grant state by reading the P_LVL2 register in the Southbridge.

If an ACPI Thermal Zone is defined for the processor, the

operating system can initiate throttling with STPCLK# using

the ACPI defined P_CNT register in the Southbridge. The

Northbridge connects the AMD Athlon system bus, and the

processor enters the Probe state to service cache snoops during

Stop Grant for C2 or throttling.