AMD AXDA3200DKV4E Data Sheet - Page 39

26237C-May 2003 Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 7.3 Advanced 400 FSB AMD Athlon™ System Bus AC Characteristics The AC characteristics of the AMD Athlon system bus of this processor are shown in Table 7. The parameters are grouped based on the source or destination of the signals involved. Table 7. Advanced 400 FSB AMD Athlon™ System Bus AC Characteristics Group Symbol Parameter Min Max Units Notes All Signals TRISE TFALL Output Rise Slew Rate Output Fall Slew Rate 1 3 V/ns 1 1 3 V/ns 1 TSKEW-DIFFEDGE Output skew with respect to a different clock edge - 500 ps 2 Forward TSU Clocks THD Input Data Setup Time 300 Input Data Hold Time 300 ps 3 ps 3 CIN Capacitance on input clocks 4 25 pF COUT Capacitance on output clocks 4 12 pF TVAL RSTCLK to Output Valid 800 2000 ps 4, 5 Sync TSU Setup to RSTCLK 500 ps 4, 6 THD Hold from RSTCLK 500 ps 4, 6 Notes: 1. Rise and fall time ranges are guidelines over which the I/O has been characterized. 2. TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to different clock edges. 3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock. 4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST. 5. TVAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF. 6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of RSTCLK. Chapter 7 Advanced 400 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications 27