AMD AXDA3200DKV4E Data Sheet - Page 55
Signal and PowerUp Requirements, 9.1 PowerUp Requirements, Signal Sequence and Timing Description
View all AMD AXDA3200DKV4E manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 55 highlights
26237C-May 2003 Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 9 Signal and Power-Up Requirements The AMD Athlon™ XP processor model 10 is designed to provide functional operation if the voltage and temperature parameters are within the limits of normal operating ranges. 9.1 Power-Up Requirements Signal Sequence and Timing Description Figure 13 shows the relationship between key signals in the system during a power-up sequence. This figure details the requirements of the processor. 3.3 V Supply VCCA (2.5 V) (for PLL) VCC_CORE RESET# NB_RESET# PWROK FID[3:0] System Clock 2 1 6 4 5 7 3 Warm reset condition 8 Figure 13. Signal Relationship Requirements During Power-Up Sequence Notes: 1. Figure 13 represents several signals generically by using names not necessarily consistent with any pin lists or schematics. 2. Requirements 1-8 in Figure 13 are described in "Power-Up Timing Requirements" on page 44. Chapter 9 Signal and Power-Up Requirements 43